IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 16

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–4
Simulate the System
MegaWizard Plug-In Manager Flow
DDR and DDR2 SDRAM High-Performance Controller User Guide
f
f
1
8. For this example system, ensure all the other modules are clocked on the
9. Click Generate.
10. Compile your design, refer to
During system generation, SOPC Builder optionally generates a simulation model
and testbench for the entire system, which you can use to easily simulate your system
in any of Altera's supported simulation tools. SOPC Builder also generates a set of
ModelSim
functional simulation models, and plain-text RTL design files that describe your
system in the ModelSim simulation software.
For more information about simulating SOPC Builder systems, refer to
the Quartus II Handbook and
The MegaWizard Plug-In Manager flow allows you to customize the DDR and DDR2
SDRAM High-Performance Controller MegaCore function, and manually integrate
the function into your design.
You can alternatively use the IP Advisor to help you start your DDR and DDR2
SDRAM High-Performance Controller MegaCore design. On the Quartus II Tools
menu, point to Advisors, and then click IP Advisor. The IP Advisor guides you
through a series of recommendations for selecting, parameterizing, evaluating, and
instantiating a DDR and DDR2 SDRAM High-Performance Controller MegaCore
function into your design. It then guides you through a complete Quartus II
compilation of your project.
For more information about the MegaWizard Plug-In Manager and the IP Advisor,
refer to the Quartus II Help.
altmemddr_sysclk, to avoid any unnecessary clock-domain crossing logic.
1
c
If you are upgrading your Nios system design from version 8.1 or previous ,
ensure that you change the Reset Vector Offset and the Exception Vector
Offset to AFI mode.
Among the files generated by SOPC Builder is the Quartus II IP File (.qip).
This file contains information about a generated IP core or system. In most
cases, the .qip file contains all of the necessary assignments and
information required to process the MegaCore function or system in the
Quartus II compiler. Generally, a single .qip file is generated for each SOPC
Builder system. However, some more complex SOPC Builder components
generate a separate .qip file. In that case, the system .qip file references the
component .qip file.
®
Tcl scripts and macros that you can use to compile the testbench, IP
AN 351: Simulating Nios II
“Compile the Design” on page
Systems.
© March 2009 Altera Corporation
MegaWizard Plug-In Manager Flow
2–13.
Chapter 2: Getting Started
volume 4
of