IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 59

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
© March 2009 Altera Corporation
8. The controller returns the first read data to the user by asserting the
9. The controller issues a PCH command to close current memory row (0x0000) and
10. The ALTMEMPHY megafunction issues the PCH commands to the memory.
11. The controller issues an ACT command to open the next memory row (0x0008).
12. The ALTMEMPHY megafunction issues the ACT commands to the memory.
13. The controller issues the second read memory command and column address
14. The ALTMEMPHY megafunction issues the read commands to the memory.
15. The controller returns the second read data to the user by asserting the
Full Rate, Native Interface Mode—Alternate Read-Write
Figure 4–12 on page 4–32
and using the Local Interface Protocol setting set to Native interface.
local_rdata_valid signal when there is valid read data on the local_rdata
bus. If Enable error correction and detection logic is disabled, there is no delay
between the control_rdata and the local_rdata buses. If there is ECC logic
in the controller, there is one or three clock cycles of delay between the
control_rdata and local_rdata buses.
allow the second read to a different memory row (0x0008).
(0x0008) to the ALTMEMPHY megafunction for it to send to the memory device.
local_rdata_valid signal when there is valid read data on the local_rdata
bus.
shows read, write, read, write operation in full-rate mode
DDR and DDR2 SDRAM High-Performance Controller User Guide
4–31