IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 52

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–24
DDR and DDR2 SDRAM High-Performance Controller User Guide
mem_dq
mem_dm
=
=
<55>
<1>
The following sequence corresponds with the numbered items in
page
1. The user logic requests the first write by asserting the local_write_req signal,
2. The user logic requests a second write to a sequential address of size 1 (4 on the
3. The controller requests the write data and byte enables for the write from the user
4. The user logic to a sequential address, again of size 1. The controller is able to
5. The controller issues the necessary memory command and address signals to the
6. The controller asserts the control_wdata_valid signal to indicate to the
7. The controller asserts the control_dqs_burst signals to control the timing of
8. The ALTMEMPHY megafunction issues the write command and sends the write
local_wdata =
local_be =
<44>
and the size and address for this write. In this example, the request is a burst of
length 1 (4 on the memory side) address 0. The local_ready signal is asserted,
which indicates that the controller has accepted this request, and the user logic can
request another read or write in the following clock cycle. If the local_ready
signal was not asserted, the user logic must keep the write request, size, and
address signals asserted until the local_ready signal is registered high.
These values map to::
memory side). The local_ready signal remains asserted, which indicates that
the controller has accepted the request. The address increments by the local burst
size.
logic. The write data and byte enables must be presented in the clock cycle after
the request. In this example, the controller also continues to request write data for
the subsequent writes. The user logic must be able to supply the write data for the
entire burst when it requests a write.
buffer up to four requests so the local_ready signal stays high and the request
is accepted.
ALTMEMPHY megafunction for it to send to the memory device.
ALTMEMPHY megafunction that valid write data and write data masks are
present on the inputs to the ALTMEMPHY megafunction.
the DQS signal that the ALTMEMPHY megafunction issues to the memory.
f
data and write DQS to the memory.
<1>
4–23.
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<0>
Refer to the “Handshake Mechanism Between Write Commands and
Write Data” section of the
User Guide (ALTMEMPHY)
<22>
<0>
<AA>
<1>
<22334455>
<1100>
<88>
<0>
External Memory PHY Interface Megafunction
for more details of this interface.
<77>
<0>
<667788AA>
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<1>
<0110>
<EE>
<1>
Chapter 4: Functional Description
© March 2009 Altera Corporation
<DD>
<0>
Figure 4–8 on
<BBCCDDEE>
Interfaces and Signals
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<CC>
<1>
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