IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 76

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–4
The Testbench Stages
Table 5–1. Stages of Operation
Memory Device Initialization
DDR and DDR2 SDRAM High-Performance Controller User Guide
PLL initialization and lock
Memory device initialization
Interface training and calibration
Functional memory use
f
Stages of Operation
6. ModelSim-AE includes all Altera device libraries; so a .do script for ModelSim-AE
Before the user logic (example driver) can read or write to the local interface, the
external SDRAM must first be initialized and calibrated. Following power-up or a
reset event, the following stages of operation take place.
each stage takes place, depending on the controller/PHY interface selected.
The following sections discuss the stages that take place in the controller.
For more information for operations that take place in the PHY, refer to the
Memory PHY Interface Megafunction User Guide
In non-AFI mode, memory devices must be initialized before functional use. The
exact sequence is different for DDR2 and DDR. The memory controller sets the
operating parameters of the memory based on the parameters you specify in the
MegaWizard interface. This parameter is fixed at generation time and is not
dynamically editable via the local interface.
Figure 5–2 on page 5–6
the NOP command where t
simulation.
The exact sequence of commands differs between the various external memory
families (refer to the respective the device datasheets for further information). For this
DDR2 SDRAM example, the following sequence applies:
1. Issue NOP commands for 200 µs, programmable via t
2. Assert mem_cke (high).
3. Issue a PCH, then wait for 400 ns after t
4. Issue an LMR command to ELMR register 2 = 0.
5. Issue an LMR command to ELMR register 3 = 0.
does not compile these libraries. NativeLink includes the relevant libraries for
other simulators.
f
counter by 500).
Refer to
Altera-supported RTL simulation tools.
Simulation and Verification Support Resources
shows the memory initialization stage which is dominated by
INIT
is 200 µs. The controller automatically skips t
AFI Mode
Controller
PHY
PHY
PHY
INIT
(400 ns is derived from dividing t
(ALTMEMPHY).
Chapter 5: Example Design Walkthrough
Table 5–1
INIT
parameter.
© March 2009 Altera Corporation
if you use other
Non-AFI Mode
indicates where
Controller
Controller
PHY
PHY
The Testbench Stages
External
INIT
in
INIT