IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 41

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Example Design
© March 2009 Altera Corporation
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The example driver has four outputs that allow you to observe which tests are
currently running and if the tests are passing. The pass not fail (pnf) signal goes low
once one or more errors occur and remains low. The pass not fail per byte
(pnf_per_byte) signal goes low when there is incorrect data in a byte but goes back
high again once correct data is observed in the following byte. The test_status
signal indicates the test that is currently running, allowing you to determine which
test has failed. The test_complete signal goes high for a single clock cycle at the
end of the set of tests.
Table 4–5
Table 4–5. Test Status[] Bit Mapping
Incomplete write operation
The state machine issues a series of write requests that are less than the maximum
burst size supported by your controller variation. The addresses are then read
back to ensure that the controller has issued the correct signals to the memory.
This test is only applicable in full-rate mode, when the local burst size is two. You
can skip this test by setting the test_incomplete_writes_on signal to logic
zero.
Byte enable/data mask pin operation
The state machine issues two sets of write commands, the first of which clears a
range of addresses. The second set of write commands has only one byte enable bit
asserted. The state machine then issues a read request to the same addresses and
the data is verified. This test checks if the data mask pins are operating correctly.
You can skip this test by setting the test_dm_pin_on signal to logic zero.
Address pin operation
The example driver generates a series of write and read requests starting with an
all-zeros pattern, a walking-one pattern, a walking-zero pattern, and ending with
an all-zeros pattern. This test checks to make sure that all the individual address
bits are operating correctly. You can skip this test by setting the
test_addr_pin_on signal to logic zero.
Low-power mode operation
The example driver requests the controller to place the memory into power-down
and self-refresh states, and hold it in those states for the amount of time specified
by the COUNTER_VALUE signal. You can vary this value to adjust the duration the
memory is kept in the low-power states. This test is only available if your
controller variation enables the low-power mode option.
Bit
shows the bit mapping for each test status.
0
1
2
3
4
5
6
Test
Sequential address test
Incomplete write test
Data mask pin test
Address pin test
Power-down test
Self-refresh test
Auto precharge test
DDR and DDR2 SDRAM High-Performance Controller User Guide
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