IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 34

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–6
Table 4–2. Typical Latency
DDR and DDR2 SDRAM High-Performance Controller User Guide
Cyclone III
Stratix III
Stratix IV
Stratix II
Arria GX
Device
1
Controller Rate
Half
Half
Half
Half
Half
■
Latency calculations are made with the following assumptions:
■
■
■
■
For the half rate controller, the local side frequency is half the memory interface
frequency; for the full rate controller, it is equal to the memory interface frequency.
Altera defines the read and write latencies in terms of the local interface clock
frequency and by the absolute time for the memory controllers.
Table 4–2
definitions for half and full rate DDR2 SDRAM high-performance controller and for
Arria GX, Cyclone III, Stratix II, Stratix III, and Stratix IV devices.
Full
Full
Full
Full
Full
Write latency is the time it takes for the write data to appear at the memory
interface after you assert the write request signal to the controller.
Reading and writing to the rows that are already open
The local_ready signal is asserted high (no wait states)
No refresh cycles occur before transaction
The latency is defined using the local side frequency and absolute time (ns)
shows the read and write latency derived from the write and read latency
Frequency
(MHz)
233
167
200
167
333
200
400
267
400
267
Controller
Latency
5
4
5
4
5
4
5
4
5
4
Latency
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Read
Read
Read
Read
Read
Read
Read
Read
Read
Read
Type
Local Clock
Cycles
Chapter 4: Functional Description
© March 2009 Altera Corporation
18
11
20
10
18
10
11
20
10
21
13
21
12
21
13
21
12
11
20
18
Total Latency
Block Description
Time
(ns)
151
120
175
105
120
105
100
111
111
91
60
60
63
50
65
85
44
65
85
44