OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 148

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
11.8 Functional description
UM10415
User manual
Fig 30. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two
a. Single frame transfer
b. Continuous/back-to-back frames transfer
Frames Transfer
DX/DR
CLK
11.8.1 Texas Instruments synchronous serial frame format
FS
Table 146: SPI/SSP interrupt Clear Register (SSP0ICR - address 0x4004 0020) bit description
Figure 30
by the SPI module.
For device configured as a master in this mode, CLK and FS are forced LOW, and the
transmit data line DX is in 3-state mode whenever the SSP is idle. Once the bottom entry
of the transmit FIFO contains data, FS is pulsed HIGH for one CLK period. The value to
be transmitted is also transferred from the transmit FIFO to the serial shift register of the
transmit logic. On the next rising edge of CLK, the MSB of the 4-bit to 16-bit data frame is
shifted out on the DX pin. Likewise, the MSB of the received data is shifted onto the DR
pin by the off-chip serial slave device.
Bit
0
1
31:2
DX/DR
CLK
FS
Symbol
RORIC
RTIC
-
MSB
shows the 4-wire Texas Instruments synchronous serial frame format supported
All information provided in this document is subject to legal disclaimers.
Description
Writing a 1 to this bit clears the “frame was received when
RxFIFO was full” interrupt.
Writing a 1 to this bit clears the Rx FIFO was not empty and
has not been read for a timeout period interrupt. The timeout
period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR
× [SCR+1]).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
4 to 16 bits
Rev. 1 — 10 September 2010
MSB
LSB
4 to 16 bits
MSB
LSB
4 to 16 bits
Chapter 11: EM773 SPI0 with SSP
LSB
UM10415
© NXP B.V. 2010. All rights reserved.
Reset Value
NA
NA
NA
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