OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 180

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
UM10415
User manual
14.7.1 Watchdog Mode register (WDMOD - 0x4000 0000)
Table 168. Register overview: Watchdog timer (base address 0x4000 4000)
[1]
The WDMOD register controls the operation of the Watchdog through the combination of
WDEN and RESET bits. Note that a watchdog feed must be performed before any
changes to the WDMOD register take effect.
Table 169. Watchdog Mode register (WDMOD - address 0x4000 4000) bit description
Once the WDEN and/or WDRESET bits are set, they can not be cleared by software. Both
flags are cleared by a reset or a Watchdog timer underflow.
WDTOF The Watchdog time-out flag is set when the Watchdog times out. This flag is
cleared by software or a POR or Brown-Out-Detect reset.
WDINT The Watchdog interrupt flag is set when the Watchdog times out. This flag is
cleared when any reset occurs. Once the watchdog interrupt is serviced, it can be
disabled in the NVIC or the watchdog interrupt request will be generated indefinitely. The
intent of the watchdog interrupt is to allow debugging watchdog activity without resetting
the device when the watchdog overflows.
Watchdog reset or interrupt will occur any time the watchdog is running and has an
operating clock source. Any clock source works in Sleep mode, and if a watchdog
interrupt occurs in Sleep mode, it will wake up the device.
Name
WDMOD
WDTC
WDFEED
WDTV
Bit
0
1
2
3
7:4
31:8 -
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Symbol
WDEN
WDRESET WDRESET Watchdog reset enable bit (Set Only). When 1,
WDTOF
WDINT
-
Access Address
R/W
R/W
WO
RO
All information provided in this document is subject to legal disclaimers.
Description
WDEN Watchdog enable bit (Set Only). When 1, the
watchdog timer is running.
a watchdog time-out will cause a chip reset.
WDTOF Watchdog time-out flag. Set when the watchdog
timer times out, cleared by software.
WDINT Watchdog interrupt flag (Read Only, not clearable
by software).
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
reserved
Rev. 1 — 10 September 2010
offset
0x000
0x004
0x008
0x00C
Description
Watchdog mode register. This register contains the
basic mode and status of the Watchdog Timer.
Watchdog timer constant register. This register
determines the time-out value.
Watchdog feed sequence register. Writing 0xAA
followed by 0x55 to this register reloads the
Watchdog timer with the value contained in WDTC.
Watchdog timer value register. This register reads
out the current value of the Watchdog timer.
Chapter 14: EM773 WatchDog Timer (WDT)
UM10415
© NXP B.V. 2010. All rights reserved.
Reset Value
0
0
0 (Only after
POR and BOD
reset)
0
NA
-
180 of 310
Reset
Value
0
0xFF
NA
0xFF
[1]