OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 73

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
9.5 Clocking and power control
9.6 Register description
Table 89.
UM10415
User manual
Name
U0RBR
U0THR
U0DLL
U0DLM
U0IER
U0IIR
U0FCR
U0LCR
U0MCR
U0LSR
U0MSR
U0SCR
U0ACR
-
U0FDR
-
Register overview: UART (base address: 0x4000 8000)
Access Address
RO
WO
R/W
R/W
R/W
RO
WO
R/W
R/W
RO
RO
R/W
R/W
-
R/W
-
The UART block is gated by the AHBCLKCTRL register (see
UART clock, which is used by the UART baud rate generator, is controlled by the
UARTCLKDIV register (see
The UART_PCLK can be disabled in the UARTCLKDIV register (see
UART block can be disabled through the System AHB clock control register bit 12 (see
Table
Remark: The UART pins must be configured in the corresponding IOCON registers
before the UART clocks are enabled.
The UART contains registers organized as shown in
Bit (DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches.
offset
0x000
0x000
0x000
0x004
0x004
0x008
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
17) for power savings.
Description
Receiver Buffer Register. Contains the next received character
to be read.
Transmit Holding Register. The next character to be transmitted
is written here.
Divisor Latch LSB. Least significant byte of the baud rate
divisor value. The full divisor is used to generate a baud rate
from the fractional rate divider.
Divisor Latch MSB. Most significant byte of the baud rate
divisor value. The full divisor is used to generate a baud rate
from the fractional rate divider.
Interrupt Enable Register. Contains individual interrupt enable
bits for the 7 potential UART interrupts.
Interrupt ID Register. Identifies which interrupt(s) are pending.
FIFO Control Register. Controls UART FIFO usage and modes. 0x00
Line Control Register. Contains controls for frame formatting
and break generation.
Modem control register
Line Status Register. Contains flags for transmit and receive
status, including line errors.
Modem status register
Scratch Pad Register. Eight-bit temporary storage for software. 0x00
Auto-baud Control Register. Contains controls for the
auto-baud feature.
Reserved
Fractional Divider Register. Generates a clock input for the
baud rate divider.
Reserved
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
Chapter 9: EM773 Universal Asynchronous Transmitter (UART)
Table
19).
Table
89. The Divisor Latch Access
Table
17). The peripheral
Table
UM10415
-
-
Reset
Value
NA
NA
0x01
0x00
0x00
0x01
0x00
0x00
0x60
0x00
0x00
0x10
© NXP B.V. 2010. All rights reserved.
19) and the
[1]
Notes
when
DLAB=0
when
DLAB=0
when
DLAB=1
when
DLAB=1
when
DLAB=0
-
-
-
-
-
-
-
-
-
-
-
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