OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 307

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
18.2.3
18.2.4
18.2.5
18.2.6
18.2.7
18.2.7.1
18.3
18.3.1
18.3.2
18.3.3
18.3.4
18.3.5
18.3.6
18.3.7
18.3.8
18.3.9
18.4
18.4.1
18.4.2
18.4.3
18.4.4
18.4.5
18.4.6
18.4.7
Chapter 19: EM773 Serial Wire Debug (SWD)
19.1
19.2
19.3
Chapter 20: Appendix EM773 ARM Cortex-M0 reference
20.1
20.2
20.2.1
20.2.2
20.2.3
20.2.4
20.3
20.3.1
20.3.1.1
20.3.1.2
20.3.1.3
20.3.1.3.1 General-purpose registers . . . . . . . . . . . . . . 228
20.3.1.3.2 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . 228
20.3.1.3.3 . . . . . . . . . . . . . . . . . . . . . . . . .Link Register 229
20.3.1.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . 229
20.3.1.3.5 Program Status Register . . . . . . . . . . . . . . . 229
20.3.1.3.6 Exception mask register . . . . . . . . . . . . . . . . 231
20.3.1.3.7 CONTROL register . . . . . . . . . . . . . . . . . . . . 231
20.3.1.4
UM10415
User manual
UART Communication protocol . . . . . . . . . . 206
UART ISP commands . . . . . . . . . . . . . . . . . . 208
How to read this chapter . . . . . . . . . . . . . . . . 223
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 225
About the Cortex-M0 processor and core
peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Criterion for Valid User Code . . . . . . . . . . . . 202
Boot process flowchart . . . . . . . . . . . . . . . . . 203
Sector numbers . . . . . . . . . . . . . . . . . . . . . . 203
Flash content protection mechanism . . . . . . 204
Code Read Protection (CRP) . . . . . . . . . . . . 204
ISP entry protection . . . . . . . . . . . . . . . . . . . 206
UART ISP command format . . . . . . . . . . . . . 207
UART ISP response format . . . . . . . . . . . . . 207
UART ISP data format . . . . . . . . . . . . . . . . . 207
UART ISP flow control . . . . . . . . . . . . . . . . . 207
UART SP command abort . . . . . . . . . . . . . . 207
Interrupts during UART ISP . . . . . . . . . . . . . 207
Interrupts during IAP. . . . . . . . . . . . . . . . . . . 207
RAM used by ISP command handler . . . . . . 208
RAM used by IAP command handler . . . . . . 208
Unlock <Unlock code> (UART ISP) . . . . . . . 209
Set Baud Rate <Baud Rate> <stop bit> (UART
ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Echo <setting> (UART ISP) . . . . . . . . . . . . . 209
Write to RAM <start address> <number of bytes>
(UART ISP). . . . . . . . . . . . . . . . . . . . . . . . . . 209
Read Memory <address> <no. of bytes> (UART
ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Prepare sector(s) for write operation <start sector
number> <end sector number> (UART ISP) 211
Copy RAM to flash <Flash address> <RAM
address> <no of bytes> (UART ISP) . . . . . . 211
System-level interface . . . . . . . . . . . . . . . . . 226
Integrated configurable debug . . . . . . . . . . . 226
Cortex-M0 processor features summary . . . 226
Cortex-M0 core peripherals . . . . . . . . . . . . . 226
Programmers model . . . . . . . . . . . . . . . . . . . 227
Processor modes . . . . . . . . . . . . . . . . . . . . . 227
Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Core registers . . . . . . . . . . . . . . . . . . . . . . . 227
Exceptions and interrupts . . . . . . . . . . . . . . . 232
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
18.4.8
18.4.9
18.4.10
18.4.11
18.4.12
18.4.13
18.4.14
18.4.15
18.5
18.5.1
18.5.2
18.5.3
18.5.4
18.5.5
18.5.6
18.5.7
18.5.8
18.5.9
18.5.10
18.6
18.6.1
18.6.2
18.7
19.4
19.5
19.6
20.3.1.5
20.3.1.6
20.3.2
20.3.2.1
20.3.2.2
20.3.2.3
20.3.2.4
20.3.2.5
20.3.2.5.1 Little-endian format . . . . . . . . . . . . . . . . . . . 237
20.3.3
20.3.3.1
20.3.3.2
20.3.3.3
20.3.3.4
20.3.3.5
20.3.3.6
20.3.3.6.1 Exception entry . . . . . . . . . . . . . . . . . . . . . . 241
20.3.3.6.2 Exception return. . . . . . . . . . . . . . . . . . . . . . 242
Chapter 21: EM773 Supplementary information
IAP commands . . . . . . . . . . . . . . . . . . . . . . . 215
Debug notes . . . . . . . . . . . . . . . . . . . . . . . . . 221
Flash memory access. . . . . . . . . . . . . . . . . . 222
Description . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Pin description . . . . . . . . . . . . . . . . . . . . . . . 223
Debug Notes . . . . . . . . . . . . . . . . . . . . . . . . . 224
Go <address> <mode> (UART ISP) . . . . . . 212
Erase sector(s) <start sector number> <end
sector number> (UART ISP) . . . . . . . . . . . . 212
Blank check sector(s) <sector number> <end
sector number> (UART ISP) . . . . . . . . . . . . 213
Read Part Identification number (UART ISP) 213
Read Boot code version number (UART ISP) 213
Compare <address1> <address2> <no of bytes>
(UART ISP) . . . . . . . . . . . . . . . . . . . . . . . . . 214
ReadUID (UART ISP) . . . . . . . . . . . . . . . . . 214
UART ISP Return Codes . . . . . . . . . . . . . . . 214
Prepare sector(s) for write operation (IAP) . 217
Copy RAM to flash (IAP) . . . . . . . . . . . . . . . 218
Erase Sector(s) (IAP). . . . . . . . . . . . . . . . . . 218
Blank check sector(s) (IAP) . . . . . . . . . . . . . 219
Read Part Identification number (IAP) . . . . . 219
Read Boot code version number (IAP) . . . . 219
Compare <address1> <address2> <no of bytes>
(IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Reinvoke ISP (IAP) . . . . . . . . . . . . . . . . . . . 220
ReadUID (IAP) . . . . . . . . . . . . . . . . . . . . . . . 220
IAP Status Codes. . . . . . . . . . . . . . . . . . . . . 221
Comparing flash images . . . . . . . . . . . . . . . 221
Serial Wire Debug (SWD) flash programming
interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Data types . . . . . . . . . . . . . . . . . . . . . . . . . . 232
The Cortex Microcontroller Software Interface
Standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Memory model . . . . . . . . . . . . . . . . . . . . . . . 233
Memory regions, types and attributes . . . . . 234
Memory system ordering of memory accesses . .
235
Behavior of memory accesses . . . . . . . . . . 235
Software ordering of memory accesses. . . . 236
Memory endianness. . . . . . . . . . . . . . . . . . . 237
Exception model . . . . . . . . . . . . . . . . . . . . . 237
Exception states. . . . . . . . . . . . . . . . . . . . . . 237
Exception types . . . . . . . . . . . . . . . . . . . . . . 238
Exception handlers . . . . . . . . . . . . . . . . . . . 239
Vector table . . . . . . . . . . . . . . . . . . . . . . . . . 239
Exception priorities. . . . . . . . . . . . . . . . . . . . 240
Exception entry and return. . . . . . . . . . . . . . 241
UM10415
© NXP B.V. 2010. All rights reserved.
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