OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 282

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
UM10415
User manual
20.5.2.8.1 NVIC programming hints
20.5.2.8 NVIC usage hints and tips
20.5.3 System Control Block
Ensure software uses correctly aligned register accesses. The processor does not
support unaligned accesses to NVIC registers.
An interrupt can enter pending state even if it is disabled. Disabling an interrupt only
prevents the processor from taking that interrupt.
Software uses the CPSIE i and instructions to enable and disable interrupts. The CMSIS
provides the following intrinsic functions for these instructions:
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
In addition, the CMSIS provides a number of functions for NVIC control, including:
Table 245. CMSIS functions for NVIC control
The input parameter IRQn is the IRQ number, see
more information about these functions, see the CMSIS documentation.
The System Control Block (SCB) provides system implementation information, and
system control. This includes configuration, control, and reporting of the system
exceptions. The SCB registers are:
CMSIS interrupt control function
void NVIC_EnableIRQ(IRQn_t IRQn)
void NVIC_DisableIRQ(IRQn_t IRQn)
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn)
void NVIC_SetPendingIRQ (IRQn_t IRQn)
void NVIC_ClearPendingIRQ (IRQn_t IRQn)
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority)
uint32_t NVIC_GetPriority (IRQn_t IRQn)
void NVIC_SystemReset (void)
•
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this
Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the
interrupt does not change. Otherwise, the state of the interrupt changes to inactive.
For a pulse interrupt, state of the interrupt changes to:
– inactive, if the state was pending
– active, if the state was active and pending.
is pulsed the state of the interrupt changes to pending and active. In this case,
when the processor returns from the ISR the state of the interrupt changes to
pending, which might cause the processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the
processor returns from the ISR the state of the interrupt changes to inactive.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
Chapter 20: Appendix EM773 ARM Cortex-M0 reference
Table 20–225
Description
Enable IRQn
Disable IRQn
Return true (1) if IRQn is pending
Set IRQn pending
Clear IRQn pending status
Set priority for IRQn
Read priority of IRQn
Reset the system
for more information. For
UM10415
© NXP B.V. 2010. All rights reserved.
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