OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 170

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
Table 160: Interrupt Register (TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000) bit
UM10415
User manual
Bit
3
4
31:5
description
Symbol
MR3 Interrupt
CR0 Interrupt
-
13.8.2 Timer Control Register (TMR32B0TCR and TMR32B1TCR)
13.8.3 Timer Counter (TMR32B0TC - address 0x4001 4008 and
13.8.4 Prescale Register (TMR32B0PR - address 0x4001 400C and
13.8.5 Prescale Counter Register (TMR32B0PC - address 0x4001 4010 and
The Timer Control Register (TCR) is used to control the operation of the counter/timer.
Table 161: Timer Control Register (TMR32B0TCR - address 0x4001 4004 and TMR32B1TCR -
TMR32B1TC - address 0x4001 8008)
The 32-bit Timer Counter is incremented when the Prescale Counter reaches its terminal
count. Unless it is reset before reaching its upper limit, the TC will count up through the
value 0xFFFF FFFF and then wrap back to the value 0x0000 0000. This event does not
cause an interrupt, but a Match register can be used to detect an overflow if needed.
TMR32B1PR - address 0x4001 800C)
The 32-bit Prescale Register specifies the maximum value for the Prescale Counter.
TMR32B1PC - address 0x4001 8010)
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship between the resolution
of the timer and the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale Register,
the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK.
This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when
PR = 1, etc.
Bit
0
1
31:2
Description
Interrupt flag for match channel 3.
Interrupt flag for capture channel 0 event.
Reserved
Symbol
Counter Enable When one, the Timer Counter and Prescale Counter are
Counter Reset
-
address 0x4001 8004) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
Description
enabled for counting. When zero, the counters are
disabled.
When one, the Timer Counter and the Prescale Counter
are synchronously reset on the next positive edge of
PCLK. The counters remain reset until TCR[1] is
returned to zero.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Chapter 13: EM773 32-bit counter/timers (CT32B0/1)
UM10415
© NXP B.V. 2010. All rights reserved.
Reset value
0
0
-
Reset value
0
0
NA
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