OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 162

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
UM10415
User manual
12.8.12 PWM Control register (TMR16B0PWMC)
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event occurs, and the event corresponds to the one selected by
bits 1:0 in the CTCR register, will the Timer Counter register be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one half of the
PCLK clock. Consequently, duration of the HIGH/LOW levels on the same CAP input in
this case can not be shorter than 1/(2 × PCLK).
Table 155. Count Control Register (TMR16B0CTCR - address 0x4000 C070) bit description
The PWM Control Register is used to configure the match outputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).
For timer 0, three single-edge controlled PWM outputs can be selected on the
CT16B0_MAT[2:0] outputs. One additional match register determines the PWM cycle
length. When a match occurs in any of the other match registers, the PWM output is set to
HIGH. The timer is reset by the match register that is configured to set the PWM cycle
length. When the timer is reset to zero, all currently HIGH match outputs configured as
PWM outputs are cleared.
Bit
1:0
3:2
31:4
Symbol
Counter/
Timer
Mode
Count
Input
Select
-
All information provided in this document is subject to legal disclaimers.
Value
00
01
10
11
00
01
10
11
-
Rev. 1 — 10 September 2010
Description
This field selects which rising PCLK edges can increment
Timer’s Prescale Counter (PC), or clear PC and increment
Timer Counter (TC).
Timer Mode: every rising PCLK edge
Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
In counter mode (when bits 1:0 in this register are not 00),
these bits select which CAP pin is sampled for clocking:
CT16Bn_CAP0
Reserved.
Reserved.
Note: If Counter mode is selected in the CTCR register, bits
2:0 in the Capture Control Register (CCR) must be
programmed as 000.
Reserved.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 12: EM773 16-bit counter/timer (CT16B0)
UM10415
© NXP B.V. 2010. All rights reserved.
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Reset
value
00
00
NA