OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 179

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
14.5 Description
14.6 Clocking and power control
14.7 Register description
UM10415
User manual
The Watchdog consists of a divide by 4 fixed pre-scaler and a 24-bit counter. The clock is
fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value
from which the counter decrements is 0xFF. Setting a value lower than 0xFF causes 0xFF
to be loaded in the counter. Hence the minimum Watchdog interval is (T
and the maximum Watchdog interval is (T
The Watchdog should be used in the following manner:
When the Watchdog is in the reset mode and the counter underflows, the CPU will be
reset, loading the stack pointer and program counter from the vector table as in the case
of external reset. The Watchdog time-out flag (WDTOF) can be examined to determine if
the Watchdog has caused the reset condition. The WDTOF flag must be cleared by
software.
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers and is derived from the system clock (see
The WDCLK is used for the watchdog timer counting and is derived from the wdt_clk in
Figure
watchdog oscillator, and the main clock. The clock source is selected in the syscon block
(see
disable this clock.
There is some synchronization logic between these two clock domains. When the
WDMOD and WDTC registers are updated by APB operations, the new value will take
effect in 3 WDCLK cycles on the logic in the WDCLK clock domain. When the watchdog
timer is counting on WDCLK, the synchronization logic will first lock the value of the
counter on WDCLK and then synchronize it with the PCLK for reading as the WDTV
register by the CPU.
The watchdog oscillator can be powered down in the PDRUNCFG register
(Section
disabled in the AHBCLKCTRL register
Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog
oscillator frequency must be programmed by writing to the WDTOSCCTRL register (see
Table
The Watchdog contains four registers as shown in
1. Set the Watchdog timer constant reload value in WDTC register.
2. Setup the Watchdog timer operating mode in WDMOD register.
3. Enable the Watchdog by writing 0xAA followed by 0x55 to the WDFEED register.
4. The Watchdog should be fed again before the Watchdog counter underflows to
prevent reset/interrupt.
Table
9) before using the watchdog oscillator for the WDT.
3. Several clocks can be used as a clock source for wdt_clk clock: the IRC, the
3.4.33) if it is not used. The clock to the watchdog register block (PCLK) can be
20). The WDCLK has its own clock divider
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
(Table
WDCLK
Chapter 14: EM773 WatchDog Timer (WDT)
17) for power savings.
× 2
Table 168
24
(Section
× 4) in multiples of (T
below.
3.4.19), which can also
UM10415
© NXP B.V. 2010. All rights reserved.
WDCLK
WDCLK
Figure
× 256 × 4)
179 of 310
× 4).
3).