OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 65

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

8.1 How to read this chapter
Table 77.
8.2 Introduction
8.3 Register description
Table 78.
UM10415
User manual
Part
EM773
Name
GPIOnDATA
GPIOnDATA
-
GPIOnDIR
GPIOnIS
GPIOnIBE
GPIOnIEV
GPIOnIE
GPIO configuration
Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000;
port 3: 0x5003 0000)
Package
HVQFN33 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0
8.2.1 Features
The number of GPIO pins available on each port depends on the EM773 part and the
package. See
Register bits corresponding to PIOn_m pins which are not available are reserved.
Each GPIO register can be up to 12 bits wide and can be read or written using word or
half-word operations at word addresses.
GPIO port 0
•
•
•
•
•
•
UM10415
Chapter 8: EM773 General Purpose I/O (GPIO)
Rev. 1 — 10 September 2010
GPIO pins can be configured as input or output by software.
Each individual port pin can serve as an edge or level-sensitive interrupt request.
Interrupts can be configured on single falling or rising edges and on both edges.
Level-sensitive interrupt pins can be HIGH or LOW-active.
All GPIO pins are inputs by default.
Reading and writing of data registers are masked by address bits 13:2.
Access
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
Table 77
All information provided in this document is subject to legal disclaimers.
Address offset
0x0000 to 0x3FF8
0x3FFC
0x4000 to 0x7FFC
0x8000
0x8004
0x8008
0x800C
0x8010
GPIO port 1
Rev. 1 — 10 September 2010
for available GPIO pins:
Description
Port n data address masking register
locations for pins PIOn_0 to PIOn_11 (see
Section
Port n data register for pins PIOn_0 to
PIOn_11
reserved
Data direction register for port n
Interrupt sense register for port n
Interrupt both edges register for port n
Interrupt event register for port n
Interrupt mask register for port n
GPIO port 2
8.4.1).
GPIO port 3
PIO3_2; PIO3_4; PIO3_5 28
© NXP B.V. 2010. All rights reserved.
User manual
Reset
value
n/a
n/a
-
0x00
0x00
0x00
0x00
0x00
65 of 310
Total
GPIO
pins