OM13005,598 NXP Semiconductors, OM13005,598 Datasheet - Page 278

• Manufacturer Part Number: OM13005,598
• Description: BOARD EVAL EM773 METER US PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13005,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6680

NXP Semiconductors
Table 239. CMISIS access NVIC functions
[1]
UM10415
User manual
CMSIS function
void NVIC_EnableIRQ(IRQn_Type IRQn)
void NVIC_DisableIRQ(IRQn_Type IRQn)
void NVIC_SetPendingIRQ(IRQn_Type IRQn)
void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
The input parameter IRQn is the IRQ number, see
20.5.2.1 Accessing the Cortex-M0 NVIC registers using CMSIS
20.5.2.2 Interrupt Set-enable Register
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
The hardware implementation of the NVIC registers is:
Table 238. NVIC register summary
CMSIS functions enable software portability between different Cortex-M profile
processors.
To access the NVIC registers when using CMSIS, use the following functions:
The ISER enables interrupts, and shows which interrupts are enabled. See the register
summary in
The bit assignments are:
Address
0xE000E100
0xE000E180
0xE000E200
0xE000E280
0xE000E400-0x
E000E41C
•
•
•
•
A programmable priority level of 0-3 for each interrupt. A higher level corresponds to a
lower priority, so level 0 is the highest interrupt priority.
Level and pulse detection of interrupt signals.
Interrupt tail-chaining.
An external Non-maskable interrupt (NMI). The NMI is not implemented on the
EM773.
Table 238
Name
ISER
ICER
ISPR
ICPR
IPR0-7
[1]
[1]
All information provided in this document is subject to legal disclaimers.
[1]
[1]
[1]
Rev. 1 — 10 September 2010
Table 225
for the register attributes.
[1]
Type
RW
RW
RW
RW
RW
[1]
Chapter 20: Appendix EM773 ARM Cortex-M0 reference
for more information.
Description
Enables an interrupt or exception.
Disables an interrupt or exception.
Sets the pending status of interrupt or exception to 1.
Clears the pending status of interrupt or exception to 0.
Reads the pending status of interrupt or exception.
This function returns non-zero value if the pending status is set
to 1.
Sets the priority of an interrupt or exception with configurable
priority level to 1.
Reads the priority of an interrupt or exception with configurable
priority level. This function returns the current priority level.
Reset value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Description
Section 20–20.5.2.2
Section 20–20.5.2.3
Section 20–20.5.2.4
Section 20–20.5.2.5
Section 20–20.5.2.6
UM10415
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