OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 102

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
10.8.2 I
10.8.3 I
10.8.4 I
The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA
is 0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge
clock pulse on the SCL line on the following situations:
Each I
Status register is Read-Only.
Table 114. I
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I
be set. For a complete list of status codes, refer to tables from
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is
always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a
byte has been received, the first bit of received data is located at the MSB of I2DAT.
Table 115. I
This register is readable and writable and are only used when an I
slave mode. In master mode, this register has no effect. The LSB of I2ADR is the General
Call bit. When this bit is set, the General Call address (0x00) is recognized.
Bit
2:0
7:3
31:8 -
Bit
7:0
31:8 -
2
2
2
2. The General Call address has been received while the General Call bit (GC) in I2ADR
3. A data byte has been received while the I
4. A data byte has been received while the I
1. A data byte has been received while the I
2. A data byte has been received while the I
C Status register (I2C0STAT - 0x4000 0004)
C Data register (I2C0DAT - 0x4000 0008)
C Slave Address register 0 (I2C0ADR0- 0x4000 000C)
is set.
Symbol Description
Data
Symbol
-
Status
2
C Status register reflects the condition of the corresponding I
2
2
C Status register (I2C0STAT - 0x4000 0004) bit description
C Data register (I2C0DAT - 0x4000 0008) bit description
This register holds data values that have been received or are to
be transmitted.
Reserved. The value read from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Description
These bits are unused and are always 0.
These bits give the actual status information about the I
interface.
Reserved. The value read from a reserved bit is not defined.
Rev. 1 — 10 September 2010
2
C states. When any of these states entered, the SI bit will
2
2
2
2
C is in the master receiver mode.
C is in the addressed slave receiver mode
C is in the master receiver mode.
C is in the addressed slave receiver mode.
Chapter 10: EM773 I2C-bus interface
Table 129
2
2
C
C interface is set to
2
C interface. The I
UM10415
© NXP B.V. 2010. All rights reserved.
to
Reset value
0
-
Table
Reset value
0
0x1F
-
102 of 310
134.
2
C