OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 273
OM13006,598
Manufacturer Part Number
OM13006,598
Description
BOARD EVAL EM773 METER EU PLUG
Manufacturer
NXP Semiconductors
Type
Other Power Managementr
Specifications of OM13006,598
Design Resources
Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
Main Purpose
Power Management, Energy/Power Meter
Embedded
Yes, MCU, 32-Bit
Utilized Ic / Part
EM773FHN33,551
Interface Type
USB
Maximum Operating Temperature
+ 150 C
Operating Supply Voltage
1.8 V to 3.6 V
Product
Power Management Development Tools
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Primary Attributes
-
Secondary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
EM773, OL2381
Other names
568-6681
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UM10415
User manual
20.4.7.4.4 Condition flags
20.4.7.4.5 Examples
20.4.7.5.1 Syntax
20.4.7.5.2 Operation
20.4.7.5.3 Restrictions
20.4.7.5.4 Condition flags
20.4.7.5.5 Examples
20.4.7.6.1 Syntax
20.4.7.6.2 Operation
20.4.7.6.3 Restrictions
20.4.7.5 ISB
20.4.7.6 MRS
This instruction does not change the flags.
Instruction Synchronization Barrier.
ISB
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor,
so that all instructions following the ISB are fetched from cache or memory again, after the
ISB instruction has been completed.
There are no restrictions.
This instruction does not change the flags.
Move the contents of a special register to a general-purpose register.
MRS Rd, spec_reg
where:
MRS stores the contents of a special-purpose register to a general-purpose register. The
MRS instruction can be combined with the MR instruction to produce read-modify-write
sequences, which are suitable for modifying a specific flag in the PSR.
See
In this instruction, Rd must not be SP or PC.
Rd is the general-purpose destination register.
spec_reg is one of the special-purpose registers: APSR, IPSR, EPSR, IEPSR, IAPSR,
EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.
DSB ; Data Synchronisation Barrier
ISB ; Instruction Synchronisation Barrier
Section
20–20.4.7.7.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
Chapter 20: Appendix EM773 ARM Cortex-M0 reference
UM10415
© NXP B.V. 2010. All rights reserved.
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