OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 78

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
The UART RDA interrupt (U0IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (U0IIR[3:1] = 110). The RDA is activated when the UART Rx FIFO reaches the
trigger level defined in U0FCR7:6 and is reset when the UART Rx FIFO depth falls below
the trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (U0IIR[3:1] = 110) is a second level interrupt and is set when the UART
Rx FIFO contains at least one character and no UART Rx FIFO activity has occurred in
3.5 to 4.5 character times. Any UART Rx FIFO activity (read or write of UART RSR) will
clear the interrupt. This interrupt is intended to flush the UART RBR after a message has
been received that is not a multiple of the trigger level size. For example, if a peripheral
wished to send a 105 character message and the trigger level was 10 characters, the
CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5
CTI interrupts (depending on the service routine) resulting in the transfer of the remaining
5 characters.
Table 96.
[1]
[2]
[3]
[4]
The UART THRE interrupt (U0IIR[3:1] = 001) is a third level interrupt and is activated
when the UART THR FIFO is empty provided certain initialization conditions have been
met. These initialization conditions are intended to give the UART THR FIFO a chance to
fill up with data to eliminate many THRE interrupts from occurring at system start-up. The
U0IIR[3:0]
value
0001
0110
0100
1100
0010
Values “0000”, “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
For details see
For details see
Read Only)”
For details see
and
Only)”
[1]
Section 9.6.2 “UART Transmitter Holding Register (U0THR - 0x4000 8000 when DLAB = 0, Write
UART Interrupt Handling
Priority Interrupt
-
Highest RX Line
Second RX Data
Second Character
Third
All information provided in this document is subject to legal disclaimers.
Section 9.6.9 “UART Line Status Register (U0LSR - 0x4000 8014, Read Only)”
Section 9.6.1 “UART Receiver Buffer Register (U0RBR - 0x4000 8000, when DLAB = 0,
Section 9.6.5 “UART Interrupt Identification Register (U0IIR - 0x4004 8008, Read Only)”
type
None
Status /
Error
Available
Time-out
indication
THRE
Rev. 1 — 10 September 2010
Chapter 9: EM773 Universal Asynchronous Transmitter (UART)
Interrupt source
None
OE
Rx data available or trigger level reached in FIFO
(U0FCR0=1)
Minimum of one character in the RX FIFO and no
character input or removed during a time period
depending on how many characters are in FIFO
and what the trigger level is set at (3.5 to 4.5
character times).
The exact time will be:
[(word length) × 7 - 2] × 8 + [(trigger level - number
of characters) × 8 + 1] RCLKs
THRE
[2]
or PE
[2]
[2]
or FE
[2]
or BI
[2]
UM10415
© NXP B.V. 2010. All rights reserved.
Interrupt
reset
-
U0LSR
Read
U0RBR
Read
UART FIFO
drops below
trigger level
U0RBR
Read
U0IIR
Read
source of
interrupt) or
THR write
78 of 310
[2]
[3]
[3]
[4]
or
(if