OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 235

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
20.3.2.2 Memory system ordering of memory accesses
20.3.2.3 Behavior of memory accesses
Strongly-ordered — The processor preserves transaction order relative to all other
transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that
the memory system can buffer a write to Device memory, but must not buffer a write to
Strongly-ordered memory.
The additional memory attributes include.
Execute Never (XN) — Means the processor prevents instruction accesses. A HardFault
exception is generated on executing an instruction fetched from an XN region of memory.
For most memory accesses caused by explicit memory access instructions, the memory
system does not guarantee that the order in which the accesses complete matches the
program order of the instructions, providing any re-ordering does not affect the behavior of
the instruction sequence. Normally, if correct program execution depends on two memory
accesses completing in program order, software must insert a memory barrier instruction
between the memory access instructions, see
However, the memory system does guarantee some ordering of accesses to Device and
Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs
before A2 in program order, the ordering of the memory accesses caused by two
instructions is:
Where:
- — Means that the memory system does not guarantee the ordering of the accesses.
< — Means that accesses are observed in program order, that is, A1 is always observed
before A2.
The behavior of accesses to each region in the memory map is:
Fig 56. Memory ordering restrictions
Device access, non-shareable
A1
Device access, shareable
Strongly-ordered access
All information provided in this document is subject to legal disclaimers.
Normal access
Rev. 1 — 10 September 2010
A2
Chapter 20: Appendix EM773 ARM Cortex-M0 reference
Normal
access
-
-
-
-
Non-shareable
Section
Device access
<
<
-
-
20–20.3.2.4.
Shareable
<
<
-
-
UM10415
© NXP B.V. 2010. All rights reserved.
Strongly-
ordered
access
<
<
<
-
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