OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 79

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
9.6.6 UART FIFO Control Register (U0FCR - 0x4000 8008, Write Only)
9.6.7 UART Line Control Register (U0LCR - 0x4000 800C)
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the U0THR at one time
since the last THRE = 1 event. This delay is provided to give the CPU time to write data to
U0THR without a THRE interrupt to decode and service. A THRE interrupt is set
immediately if the UART THR FIFO has held two or more characters at one time and
currently, the U0THR is empty. The THRE interrupt is reset when a U0THR write occurs or
a read of the U0IIR occurs and the THRE is the highest interrupt (U0IIR[3:1] = 001).
The U0FCR controls the operation of the UART RX and TX FIFOs.
Table 97.
The U0LCR determines the format of the data character that is to be transmitted or
received.
Table 98.
Bit
0
1
2
3
5:4
7:6
31:8 -
Bit
1:0
Symbol Value Description
Word
Length
Select
Symbol
FIFO
Enable
RX FIFO
Reset
TX FIFO
Reset
-
-
RX
Trigger
Level
UART FIFO Control Register (U0FCR - address 0x4000 8008, Write Only) bit
description
UART Line Control Register (U0LCR - address 0x4000 800C) bit description
00
01
10
11
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
-
-
00
01
10
11
Rev. 1 — 10 September 2010
5-bit character length.
6-bit character length.
7-bit character length.
8-bit character length.
Chapter 9: EM773 Universal Asynchronous Transmitter (UART)
UART FIFOs are disabled. Must not be used in the application.
Active high enable for both UART Rx and TX FIFOs and
U0FCR[7:1] access. This bit must be set for proper UART
operation. Any transition on this bit will automatically clear the
UART FIFOs.
No impact on either of UART FIFOs.
Writing a logic 1 to U0FCR[1] will clear all bytes in UART Rx FIFO,
reset the pointer logic. This bit is self-clearing.
No impact on either of UART FIFOs.
Writing a logic 1 to U0FCR[2] will clear all bytes in UART TX
FIFO, reset the pointer logic. This bit is self-clearing.
Reserved
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
These two bits determine how many receiver UART FIFO
characters must be written before an interrupt is activated.
Trigger level 0 (1 character or 0x01).
Trigger level 1 (4 characters or 0x04).
Trigger level 2 (8 characters or 0x08).
Trigger level 3 (14 characters or 0x0E).
Reserved
UM10415
© NXP B.V. 2010. All rights reserved.
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Reset
value
0
0
0
0
NA
0
-
Reset
Value
0