OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 18

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
3.4.13 System AHB clock divider register
3.4.14 System AHB clock control register
Table 15.
This register divides the main clock to provide the system clock to the core, memories,
and the peripherals. The system clock can be shut down completely by setting the DIV
bits to 0x0.
Table 16.
The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks.
The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock
for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M0, the Syscon block, and
the PMU. This clock cannot be disabled.
Table 17.
Bit
0
31:1
Bit
7:0
31:8
Bit
0
1
2
Symbol
ENA
-
Symbol
DIV
-
Symbol
SYS
ROM
RAM
Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)
bit description
System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit
description
System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
All information provided in this document is subject to legal disclaimers.
Value
0
1
to
255
-
Value
0
1
-
Rev. 1 — 10 September 2010
Value
0
1
0
1
0
1
Description
System AHB clock divider values
System clock disabled.
Divide by 1
...
Divide by 255
Reserved
Description
Enable main clock source update
No change
Update clock source
Reserved
Description
Enables clock for AHB to APB bridge, to the AHB
matrix, to the Cortex-M0 FCLK and HCLK, to the
SysCon, and to the PMU. This bit is read only.
Reserved
Enable
Enables clock for ROM.
Disable
Enable
Enables clock for RAM.
Disable
Enable
Chapter 3: EM773 System configuration
UM10415
© NXP B.V. 2010. All rights reserved.
Reset value
0x0
0x00
Reset
value
1
1
1
Reset
value
0x01
0x00
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