OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 106

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
10.8.7.2 Loss of arbitration in Monitor mode
10.8.8 I
10.8.9 I
Following all of these interrupts, the processor may read the data register to see what was
actually transmitted on the bus.
In monitor mode, the I
the bus master or issue an ACK). Some other slave on the bus will respond instead. This
will most probably result in a lost-arbitration state as far as our module is concerned.
Software should be aware of the fact that the module is in monitor mode and should not
respond to any loss of arbitration state that is detected. In addition, hardware may be
designed into the module to block some/all loss of arbitration states from occurring if those
state would either prevent a desired interrupt from occurring or cause an unwanted
interrupt to occur. Whether any such hardware will be added is still to be determined.
These registers are readable and writable and are only used when an I
to slave mode. In master mode, this register has no effect. The LSB of I2ADR is the
General Call bit. When this bit is set, the General Call address (0x00) is recognized.
Any of these registers which contain the bit 00x will be disabled and will not match any
address on the bus. All four registers will be cleared to this disabled state on reset.
Table 122. I
In monitor mode, the I
the ENA_SCL bit is not set. This means that the processor will have a limited amount of
time to read the contents of the data received on the bus. If the processor reads the I2DAT
shift register, as it ordinarily would, it could have only one bit-time to respond to the
interrupt before the received data is overwritten by new data.
To give the processor more time to respond, a new 8-bit, read-only DATA_BUFFER
register will be added. The contents of the 8 MSBs of the I2DAT shift register will be
transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus
ACK or NACK) has been received on the bus. This means that the processor will have
nine bit transmission times to respond to the interrupt and read the data before it is
overwritten.
The processor will still have the ability to read I2DAT directly, as usual, and the behavior of
I2DAT will not be altered in any way.
Although the DATA_BUFFER register is primarily intended for use in monitor mode with
the ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode of
operation.
Bit
0
7:1
31:8
2
2
C Slave Address registers (I2C0ADR[1, 2, 3] - 0x4000 00[20, 24, 28])
C Data buffer register (I2C0DATA_BUFFER - 0x4000 002C)
Address
Symbol
GC
-
description
2
C Slave Address registers (I2C0ADR[1, 2, 3]- 0x4000 00[20, 24, 28]) bit
All information provided in this document is subject to legal disclaimers.
Description
General Call enable bit.
The I
Reserved. The value read from a reserved bit is not defined.
Rev. 1 — 10 September 2010
2
2
2
C module will not be able to respond to a request for information by
C module may lose the ability to stretch the clock (stall the bus) if
C device address for slave mode.
Chapter 10: EM773 I2C-bus interface
UM10415
2
© NXP B.V. 2010. All rights reserved.
C interface is set
0
0x00
0
Reset value
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