OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 167

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
13.5 Description
13.6 Pin description
Table 157. Counter/timer pin description
13.7 Clocking and power control
13.8 Register description
UM10415
User manual
Pin
CT32B0_CAP0
CT32B0_MAT[2:0]
CT32B1_MAT[3:0]
Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and can optionally generate interrupts or perform other actions at
specified timer values based on four match registers. Each counter/timer also includes
one capture input to trap the timer value when an input signal transitions, optionally
generating an interrupt.
In PWM mode, three match registers can be used to provide a single-edge controlled
PWM output on the match output pins. One match register is used to control the PWM
cycle length.
Remark: 32-bit counter/timer0 (CT32B0) and 32-bit counter/timer1 (CT32B1) are
functionally identical except for the peripheral base address.
Table 157
The peripheral clocks (PCLK) to the 32-bit timers are provided by the system clock (see
Figure
register
32-bit counter/timer0 contains the registers shown in
contains the registers shown in
Type
Input
Output
3). These clocks can be disabled through bits 9 and 10 in the AHBCLKCTRL
(Table
gives a brief summary of each of the counter/timer related pins.
Description
Capture Signals:
A transition on a capture pin can be configured to load one of the Capture Registers
with the value in the Timer Counter and optionally generate an interrupt.
The counter/timer block can select a capture signal as a clock source instead of the
PCLK derived clock. For more details see
(TMR32B0CTCR and TMR32B1TCR)” on page
External Match Output of CT32B0/1:
When a match register TMR32B0/1MR3:0 equals the timer counter (TC), this output
can either toggle, go LOW, go HIGH, or do nothing. The External Match Register
(EMR) and the PWM Control register (PWMCON) control the functionality of this
output.
17) for power savings.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
Table
Chapter 13: EM773 32-bit counter/timers (CT32B0/1)
159. More detailed descriptions follow.
Section 13.8.11 “Count Control Register
Table 158
173.
and 32-bit counter/timer1
UM10415
© NXP B.V. 2010. All rights reserved.
167 of 310