OM13006,598 NXP Semiconductors, OM13006,598 Datasheet - Page 287

• Manufacturer Part Number: OM13006,598
• Description: BOARD EVAL EM773 METER EU PLUG
• Manufacturer: NXP Semiconductors
• Type: Other Power Managementr

Specifications of OM13006,598

• Design Resources: Plug Meter Schematics, Gerber Files USB Dongle Schematics, Gerber Files
• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: EM773FHN33,551
• Interface Type: USB
• Maximum Operating Temperature: + 150 C
• Operating Supply Voltage: 1.8 V to 3.6 V
• Product: Power Management Development Tools
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: EM773, OL2381
• Other names: 568-6681

NXP Semiconductors
UM10415
User manual
20.5.3.7.1 System Handler Priority Register 2
20.5.3.6 Configuration and Control Register
20.5.3.7 System Handler Priority Registers
The CCR is a read-only register and indicates some aspects of the behavior of the
Cortex-M0 processor. See the register summary in
The bit assignments are:
Table 251. CCR bit assignments
The SHPR2-SHPR3 registers set the priority level, 0 to 3, of the exception handlers that
have configurable priority.
SHPR2-SHPR3 are word accessible. See the register summary in
attributes.
To access to the system exception priority level using CMSIS, use the following CMSIS
functions:
The input parameter IRQn is the IRQ number, see
The system fault handlers, and the priority field and register for each handler are:
Table 252. System fault handler priority fields
Each PRI_N field is 8 bits wide, but the processor implements only bits[7:6] of each field,
and bits[5:0] read as zero and ignore writes.
The bit assignments are:
Bits
[31:10]
[9]
[8:4]
[3]
[2:0]
Handler
SVCall
PendSV
SysTick
•
•
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Name
-
STKALIGN
-
UNALIGN_TRP
-
Field
PRI_11
PRI_14
PRI_15
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 10 September 2010
Function
Reserved.
Always reads as one, indicates 8-byte stack alignment on
exception entry.
On exception entry, the processor uses bit[9] of the stacked PSR
to indicate the stack alignment. On return from the exception it
uses this stacked bit to restore the correct stack alignment.
Reserved.
Always reads as one, indicates that all unaligned accesses
generate a HardFault.
Reserved.
Chapter 20: Appendix EM773 ARM Cortex-M0 reference
Register description
Section 20–20.5.3.7.1
Section 20–20.5.3.7.2
Table 20–225
Table 20–246
for more information.
for the CCR attributes.
Table 20–246
UM10415
© NXP B.V. 2010. All rights reserved.
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