ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet
ADUC7032BSTZ-8L-RL
Specifications of ADUC7032BSTZ-8L-RL
Related parts for ADUC7032BSTZ-8L-RL
ADUC7032BSTZ-8L-RL Summary of contents
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FEATURES High precision analog-to-digital converters (ADCs) Dual channel, simultaneous sampling, 16-bit Σ-Δ ADCs Third independent ADC for temperature sensing Programmable ADC throughput from kHz On-chip 5 ppm/°C voltage reference Current channel Fully differential, buffered input Programmable ...
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ADuC7032-8L TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Specifications............................................................... 3 Timing Specifications .................................................................. 8 Absolute Maximum Ratings.......................................................... 14 ESD Caution................................................................................ 14 Pin Configuration and Function Descriptions........................... 15 ...
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SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3 VREF = 1.2 V internal reference; f precision oscillator. All specifications T Table 1. Parameter Test Conditions/Comments ADC SPECIFICATIONS 1 Conversion Rate Chop off, ADC normal operating mode Chop on, ...
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ADuC7032-8L Parameter Test Conditions/Comments Temperature Channel 1 No Missing Codes Valid at all ADC update rates 1 Integral Nonlinearity Offset Error Chop off, 1 LSB = 19.84 μ ...
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Parameter Test Conditions/Comments 1, 26 TEMPERATURE SENSOR Accuracy MCU in power-down or standby mode; temperature range = −40°C to −30°C MCU in power-down or standby mode; temperature range = −30°C to −16°C MCU in power-down or standby mode; temperature range ...
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ADuC7032-8L Parameter Test Conditions/Comments LIN I/O GENERAL Baud Rate VDD Supply voltage range at which the LIN interface is functional Input Capacitance LIN Comparator Response Using 22 Ω resistor 1 Time I Current limit for driver when LIN bus is ...
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Parameter Test Conditions/Comments PACKAGE THERMAL SPECIFICATIONS 31 Thermal Shutdown 32 Thermal Impedance (θ ) 48-lead LQFP, stacked die JA Top die Bottom die POWER REQUIREMENTS Power Supply Voltages VDD (Battery Supply) 33 REG_DVDD, REG_AVDD Power Consumption 34 I (MCU Normal ...
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ADuC7032-8L TIMING SPECIFICATIONS SPI Timing Specifications Table 2. SPI Master Mode Timing (PHASE Mode = 1) Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data ...
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Table 3. SPI Master Mode Timing (PHASE Mode = 0) Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data output setup time before SCLK edge ...
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ADuC7032-8L Table 4. SPI Slave Mode Timing (PHASE Mode = 1) Parameter Description SCLK edge SCLK low pulse width SL t SCLK high pulse width Data output valid after SCLK edge ...
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Table 5. SPI Slave Mode Timing (PHASE Mode = 0) Parameter Description SCLK edge SCLK low pulse width SL t SCLK high pulse width Data output valid after SCLK edge DAV ...
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ADuC7032-8L LIN Timing Specifications TxD (INPUT TO TRANSCEIVER FROM CONTROLLER) RECEIVING THRESHOLD RxD (OUTPUT OF TRANSCEIVER TO CONTROLLER TRANS_PDF BUS SIGNAL t (MEASURED FROM POINT WHEN THE REC_PDF SWITCHING THRESHOLD IS SURPASSED FALL_60% FALL_40% V SUP ...
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RECESSIVE TRANSMIT INPUT TO TRANSMITTING NODE DOMINANT TH REC (MAX) TH DOM (MAX) V SUP (TRANSCEIVER SUPPLY OF TRANSMITTING NODE) TH REC (MIN) TH DOM (MIN) RxD (OUTPUT OF RECEIVING NODE 1) RxD (OUTPUT OF RECEIVING NODE ...
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ADuC7032-8L ABSOLUTE MAXIMUM RATINGS T = −40°C to +105°C, unless otherwise noted. A Table 6. Parameter Rating AGND to DGND to VSS to IO_VSS −0 +0.3 V VBAT to AGND − +40 V VDD to VSS ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET GPIO_5/IRQ1/RxD GPIO_6/TxD GPIO_7/IRQ4 GPIO_8/IRQ5 NTRST Table 7. Pin Function Descriptions 1 Type Pin No. Mnemonic 1 RESET I 2 GPIO_5/IRQ1/RxD I/O 3 GPIO_6/TxD I/O 4 GPIO_7/IRQ4 I/O 5 GPIO_8/IRQ5 I/O PIN 1 1 IDENTIFIER ...
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ADuC7032-8L Type Pin No. Mnemonic 6 TCK I 7 TDI I 8, 34, 35 DGND S 9, 16, 17, NC 23, 25, 26, 32, 38, 39, 40, 43 TDO O 11 NTRST I 12 TMS I 13 VBAT ...
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Type Pin No. Mnemonic 36 XTAL1 O 37 XTAL2 VDD S 44 VSS S 46 RESERVED 47 IO_VSS S 48 LIN I input output supply. Description Crystal ...
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ADuC7032-8L TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC, once the ADC has settled. The Σ-Δ conversion techniques used on this part mean that while the ADC front-end signal ...
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THEORY OF OPERATION The ADuC7032- complete system solution for battery monitoring automotive applications. The device integrates all of the required features to precisely and intelligently monitor, process, and diagnose 12 V battery parameters, including battery ...
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ADuC7032-8L EmbeddedICE (I) The EmbeddedICE module provides integrated on-chip debug support for the ARM7TDMI. The EmbeddedICE module contains the breakpoint and watchpoint registers, which allow nonintrusive user code debugging. These registers are controlled through the JTAG test port. When a ...
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Interrupt Latency The worst-case latency for an FIQ consists of the following: • The longest time the request can take to pass through the synchronizer • Plus the time for the longest instruction to complete (the longest instruction is an ...
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ADuC7032-8L Remap The ARM exception vectors are all situated at the bottom of the memory array, from Address 0x00000000 to Address 0x00000020. By default, after a reset, the Flash/EE memory is logically mapped to Address 0x00000000 possible to ...
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RESET There are four kinds of reset: external reset, power-on reset, watchdog reset, and software reset. The RSTSTA register indicates the source of the last reset and can also be written by user code to initiate a software reset event. ...
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ADuC7032-8L FLASH/EE MEMORY AND THE ADUC7032-8L The ADuC7032-8L incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit repro- grammable memory space. Like EEPROM, Flash memory can be programmed in-system at the byte level, although it must first ...
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FEExHID ( protection MMR that controls read- and write-protection of the Flash/EE memory code space. If previously configured via the FEExPRO register, FEExHID may require a software key to enable access. • FEExPRO ...
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ADuC7032-8L Command Sequence for Executing a Mass Erase Because of the significance of the mass erase command, a specific code sequence must be executed to initiate this operation. 1. Set Bit 3 in FEExMOD. 2. Write 0xFFC3 in FEExADR. 3. ...
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FEE0MOD and FEE1MOD Registers Name: FEE0MOD and FEE1MOD Address: 0xFFFF0E04 and 0xFFFF0E84 Default Value (Both Registers): 0x00 Access: Read/write Function: These registers are written by user code to configure the mode of operation of the Flash/EE memory controllers. Table 16. ...
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ADuC7032-8L Block 0, Flash/EE Memory Protection Registers Name: FEE0HID and FEE0PRO Address: 0xFFFF0E20 (for FEE0HID) and 0xFFFF0E1C (for FEE0PRO) Default Value (Both Registers): 0xFFFFFFFF (for FEE0HID) and 0x00000000 (for FEE0PRO) Access: Read/write Function: These registers are written by user code ...
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In summary, there are three levels of memory protection: • Temporary protection can be set and removed by writing directly into the FEExHID MMR. This register is volatile; therefore, protection is in place only while the part remains powered on. ...
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ADuC7032-8L FLASH/EE MEMORY RELIABILITY The Flash/EE memory array on the part is fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be cycled ...
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ADUC7032-8L KERNEL The ADuC7032-8L features an on-chip kernel resident in the top the Flash/EE code space. After any reset event, this kernel copies the factory-calibrated data from the manufacturing data space into the various on-chip peripherals. The ...
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ADuC7032-8L SOFTWARE RESET PAGE ERASED? (0x14 = 0xFFFFFFFF) YES LIN RECEIVED? HANDLE LIN COMMAND RESET 1 HOUR TIMER INITIALIZE ON-CHIP PERIPHERALS TO FACTORY CALIBRATED STATE NO JTAG MODE? (NTRST = 1) NO KEY PRESENT? (0x14 = 0x27011970) NO CHECKSUM PRESENT? ...
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MEMORY MAPPED REGISTERS The memory mapped register (MMR) space is mapped into the top the MCU memory space and accessed by indirect addressing, load, and store commands through the ARM7 banked registers. An outline of the memory ...
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ADuC7032-8L COMPLETE MMR LISTING Table 20. IRQ Address Base = 0xFFFF0000 Address Name Byte Access Type 0x0000 IRQSTA 0x0004 IRQSIG 4 R 0x0008 IRQEN 4 RW 0x000C IRQCLR 4 W 0x0010 SWICFG 4 W 0x0100 FIQSTA 4 ...
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Table 23. PLL Base Address = 0xFFFF0400 Address Name Byte 0x0400 PLLSTA 4 0x0404 POWKEY0 4 0x0408 POWCON 1 0x040C POWKEY1 4 0x0410 PLLKEY0 4 0x0414 PLLCON 1 0x0418 PLLKEY1 4 0x042C OSC0TRM 1 0x0440 OSC0CON 1 0x0444 OSC0STA 1 ...
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ADuC7032-8L Table 25. UART Base Address = 0XFFFF0700 Address Name Byte 0x0700 COMTX 1 COMRX 1 COMDIV0 1 0x0704 COMIEN0 1 COMDIV1 1 0x0708 COMIID0 1 0x070C COMCON0 1 0x0710 COMCON1 1 0x0714 COMSTA0 1 0x072C COMDIV2 2 Table 26. ...
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Table 30. Flash/EE Base Address = 0xFFFF0300 Address Name Byte 0x0E00 FEE0STA 1 0x0E04 FEE0MOD 2 0x0E08 FEE0CON 1 0x0E0C FEE0DAT 2 0x0E10 FEE0ADR 2 0x0E18 FEE0SIG 3 0x0E1C FEE0PRO 4 0x0E20 FEE0HID 4 0x0E80 FEE1STA 1 0x0E84 FEE1MOD 2 ...
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ADuC7032-8L 16-BIT, SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS The ADuC7032-8L incorporates three independent Σ-Δ analog-to-digital converters (ADCs), namely, the current channel ADC (I-ADC), the voltage channel ADC (V-ADC), and the temperature channel ADC (T-ADC). These precision measurement channels integrate on-chip buffering; programmable gain ...
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VOLTAGE CHANNEL ADC (V-ADC) The V-ADC is intended to convert battery voltage. As with the current channel ADC, described in the Current Channel ADC (I-ADC) section, this ADC employs an identical Σ-Δ conversion technique, including a modified Sinc3 low-pass filter ...
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ADuC7032-8L ADC GROUND SWITCH The ADuC7032-8L features an integrated ground switch pin, GND_SW, located on Pin 15. This switch allows the user to dynamically disconnect ground from external devices. It allows either a direct connection to ground or a connection ...
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ADC NOISE PERFORMANCE TABLES Table 32, Table 33, and Table 34 show the output rms noise in microvolts (μV) for some typical output update rates on the I-, V-, and T-ADCs. The numbers are typical and are generated at a ...
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ADuC7032-8L ADC MMR INTERFACE The ADC is controlled and configured via a number of MMRs that are described in detail on the following pages. All bits defined in the top eight MSBs (Bit 8 to Bit 15) of the ADCSTA ...
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Bit Description 4 Current Channel ADC Comparator Threshold. Valid only if the current channel ADC comparator is enabled via the ADCCFG MMR. Set by hardware if the absolute value of the I-ADC conversion result exceeds the value written in the ...
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ADuC7032-8L ADC Mode Register Name: ADCMDE Address: 0xFFFF0508 Default Value: 0x00 Access: Read/write Function: The ADC Mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem. Table 36. ADCMDE MMR Bit Designations Bit Description ...
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Current Channel ADC Control Register Name: ADC0CON Address: 0xFFFF050C Default Value: 0x00002 Access: Read/write Function: The current channel ADC control MMR is a 16-bit register that is used to configure the I-ADC. Note that if the current ADC is reconfigured ...
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ADuC7032-8L Voltage Channel ADC Control Register Name: ADC1CON Address: 0xFFFF0510 Default Value: 0x0000 Access: Read/write Function: The voltage channel ADC control MMR is a 16-bit register that is used to configure the V-ADC. Note that when enabling/ disabling the voltage ...
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Bit Description Temperature Channel ADC Input Select internal temperature sensor. The temperature channel is calibrated to read 0x0000 The temperature gradient is then 16 codes per degree Celsius in twos complement or ...
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ADuC7032-8L ADC Filter Register Name: ADCFLT Address: 0xFFFF0518 Default Value: 0x0007 Access: Read/write Function: The ADC filter MMR is a 16-bit register that controls the speed and resolution of the on-chip ADCs. Note: If ADCFLT is modified, the current, voltage, ...
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Table 41. ADC Conversion Rates and Settling Times Chop Enabled Running Average Yes No Yes Yes N additional time of 60 μs per enabled ADC is required before the first ADC result is ...
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ADuC7032-8L ADC Configuration Register Name: ADCCFG Address: 0xFFFF051C Default Value: 0x00 Access: Read/write Function: The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs. Table 43. ADCCFG MMR Bit Designations Bit Description 7 Analog Ground Switch Enable. ...
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Current Channel ADC Data Register Name: ADC0DAT Address: 0xFFFF0520 Default Value: 0x0000 Access: Read only Function: This current channel ADC data MMR holds the 16-bit conversion result from the I-ADC. The ADC does not update this MMR if the ADC ...
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ADuC7032-8L Current Channel ADC Gain Calibration Register Name: ADC0GN Address: 0xFFFF053C Default Value: Part-specific, factory programmed Access: Read/write Function: This I-ADC gain MMR holds a 16-bit gain calibra- tion coefficient for scaling the I-ADC conversion result. The register is configured ...
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Current Channel ADC Threshold Count Register Name: ADC0THV Address: 0xFFFF0558 Default Value: 0x00 Access: Read only Function: This 8-bit MMR is incremented every time the absolute value of an I-ADC conversion result |I| ≥ ADC0TH. This register is decremented or ...
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ADuC7032- worth emphasizing that the I-ADC , V-ADC, and T-ADC channels can be configured to initiate periodic, normal power mode, high accuracy, single conversion cycles before returning to ADC full power-down mode. This flexibility is facilitated under full ...
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By default, the ADCFLT = 0x0007 configures the ADCs for a throughput of 1.0 kHz with all other filtering options (chop, running average, averaging factor, and Sinc3 modify) disabled. A typical filter response based on this default configuration is shown ...
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ADuC7032-8L For example, with the chop bit ADCFLT[15] set to 1, increasing the SF value (ADCFLT[6:0]) to 0x1F (31 decimal) and selecting an AF value (ADCFLT[13:8]) of 0x16 (22 decimal) results in an ADC throughput of 10 Hz. The frequency ...
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ADC Calibration As described in detail in the top level diagrams (Figure 15 and Figure 16), the signal flow through all ADC channels can be described in simple terms input voltage is applied through an input buffer (and ...
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ADuC7032-8L A factory or end-of-line calibration for the I-ADC is a two-step procedure. 1. Apply 0 A current. Configure the ADC in the required PGA setting and so on, and write to ADCMDE[2:0] to perform a system zero-scale calibration. This ...
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POWER SUPPLY SUPPORT CIRCUITS The ADuC7032-8L incorporates an on-chip, low dropout (LDO) regulator that is driven directly from the battery voltage to generate a 2.6 V internal supply. This 2.6 V supply is then used as the supply voltage for ...
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ADuC7032-8L ADuC7032-8L SYSTEM CLOCKS The ADuC7032-8L integrates a highly flexible clocking system that can be clocked from one of three sources: an integrated on- chip precision oscillator, an integrated on-chip low power oscil- lator external watch crystal. These ...
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The operating mode, clocking mode, and programmable clock divider are controlled via two MMRs, PLLCON and POWCON; and the status of the PLL is indicated by PLLSTA. PLLCON controls the operating mode of the clock system, and POWCON controls the ...
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ADuC7032-8L PLLCON Prewrite Key PLLKEY0 Name: PLLKEY0 Address: 0xFFFF0410 Access: Write only Key: 0x000000AA Function: PLLCON is a keyed register that requires a 32-bit key value to be written before and after PLLCON. PLLKEY0 is the prewrite key. PLLCON Postwrite ...
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POWCON Prewrite Key POWKEY0 Name: POWKEY0 Address: 0xFFFF0404 Access: Write only Key: 0x00000001 Function: POWCON is a keyed register that requires a 32-bit key value to be written before and after POWCON. POWKEY0 is the prewrite key. POWCON Postwrite Key ...
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ADuC7032-8L ADUC7032-8L LOW POWER CLOCK CALIBRATION The low power 131 kHz oscillator can be calibrated using either the precision 131 kHz oscillator or an external 32.768 kHz watch crystal. Two dedicated calibration counters and an oscil- lator trim register are ...
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OSC0TRM Register Name: OSC0TRM Address: 0xFFFF042C Default Value: 0xX8 Access: Read/write Function: This 8-bit register controls the low power oscillator trim. Table 48. OSC0TRM MMR Bit Designations Bit Description Reserved. Should be written as 0s ...
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ADuC7032-8L PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 16 interrupt sources on the ADuC7032-8L that are controlled by the interrupt controller. Most interrupts are generated from the on-chip peripherals such as the ADC, UART, and so on. The ARM7TDMI CPU ...
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IRQ The IRQ is the exception signal to enter the IRQ mode of the processor used to service general-purpose interrupt handling of internal and external events. There are four 32-bit registers dedicated to IRQ. IRQSIG Reflects the status ...
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ADuC7032-8L TIMERS The ADuC7032-8L features four general-purpose timers/counters. • Timer0, or lifetime timer • Timer1 • Timer2 or wake-up timer • Timer3 or watchdog timer The four timers in their normal mode of operation can be either free-running or periodic. ...
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TIMER0—LIFETIME TIMER Timer0 is a general-purpose 48-bit count-up 16-bit count- up/count-down timer with a programmable prescalar. Timer0 can be clocked from either the core clock, the low power 32.768 kHz oscillator, the precision 32.768 kHz oscillator ...
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ADuC7032-8L Timer0 Value Register Name: T0VAL0/T0VAL1 Address: 0xFFFF0304, 0xFFFF0308 Default Value: 0x0000, 0x00000000 Access: Read only Function: These are 16-bit and 32-bit registers that hold the 16 least significant bits and 32 most significant bits, respectively. T0VAL0 and T0VAL1 are ...
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TIMER1 Timer1 is a 32-bit general-purpose timer, count-down or count- up, with a programmable prescalar. The prescalar source can be the low power 32.768 kHz oscillator, the core clock, or one of two external GPIOs. This source can be scaled ...
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ADuC7032-8L Timer1 Capture Register Name: T1CAP Address: 0xFFFF0330 Default Value: 0x00000000 Access: Read/write Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event. Table 55. T1CON MMR Bit Designations Bit Description Timer1 8-Bit ...
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TIMER2—WAKE-UP TIMER Timer2 is a 32-bit wake-up timer, count-down or count-up, with a programmable prescalar. The prescalar is clocked directly from one of four clock sources, namely, the core clock (default selection), the low power 32.768 kHz oscillator, the external ...
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ADuC7032-8L Timer2 Control Register Name: T2CON Address: 0xFFFF0348 Default Value: 0x0000 Access: Read/write Function: This 32-bit MMR configures the mode of operation of Timer2. Table 56. T2CON MMR Bit Designations Bit Description Reserved Clock ...
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TIMER3—WATCHDOG TIMER LOW POWER 32.768kHz Timer3 has two modes of operation: normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. Once enabled, it requires periodic servicing to prevent it from forcing a ...
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ADuC7032-8L Timer3 Control Register Name: T3CON Address: 0xFFFF0368 Default Value: 0x0000 Access: Read/write once only Function: This 16-bit MMR configures the mode of operation of Timer3, as shown in Table 57. Table 57. T3CON MMR Bit Designations Bit Description 15 ...
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GENERAL-PURPOSE I/O The ADuC7032-8L features nine general-purpose bidirectional I/O pins (GPIO). In general, many of the GPIO pins have multiple functions that can be configured by user code. By default, the GPIO pins are configured in GPIO mode. All GPIO ...
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ADuC7032-8L Table 58. External GPIO Pin to Internal Port Signal Assignments Port GPIO Pin Port Signal Port0 GPIO_0 P0.0 IRQ0 SS GPIO_1 P0.1 SCLK GPIO_2 P0.2 MISO GPIO_3 P0.3 MOSI GPIO_4 P0.4 ECLK P0 P0.6 Port1 GPIO_5 P1.0 ...
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GPIO Port0 Control Register Name: GP0CON Address: 0xFFFF0D00 Default Value: 0x11100000 Access: Read/write Function: This 32-bit MMR selects the pin function for each Port0 pin. Table 59. GP0CON MMR Bit Designations Bit Description Reserved. These bits are ...
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ADuC7032-8L GPIO Port1 Control Register Name: GP1CON Address: 0xFFFF0D04 Default Value: 0x10000000 Access: Read/write Function: This 32-bit MMR selects the pin function for each Port1 pin. Table 60. GP1CON MMR Bit Designations Bit Description Reserved. These bits ...
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GPIO Port0 Data Register Name: GP0DAT Address: 0xFFFF0D20 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port0 (see Table 58). This register also sets the output value for GPIO pins ...
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ADuC7032-8L GPIO Port1 Data Register Name: GP1DAT Address: 0xFFFF0D30 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port1 (see Table 58). This register also sets the output value for GPIO ...
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Bit Description 22 Port2.6 Data Output. The value written to this bit appears directly on the GPIO pin assigned to P2.6 21 Port2.5 Data Output. The value written to this bit appears directly on the GPIO pin assigned to P2.5. ...
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ADuC7032-8L GPIO Port1 Set Register Name: GP1SET Address: 0xFFFF0D34 Access: Write only Function: This 32-bit MMR allows user code to individually bit address external GPIO pins to set them high only. User code can do this via the GP1SET MMR ...
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GPIO Port0 Clear Register Name: GP0CLR Address: 0xFFFF0D28 Access: Write only Function: This 32-bit MMR allows user code to individually bit address external GPIO pins to clear them low only. User code can do this via the GP0CLR MMR without ...
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ADuC7032-8L GPIO Port2 Clear Register Name: GP2CLR Address: 0xFFFF0D48 Access: Write only Function: This 32-bit MMR allows user code to individually bit address external GPIO pins to clear them low only. User code can do this via the GP2CLR MMR ...
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HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE The ADuC7032-8L integrates a number of high voltage circuit functions that are controlled and monitored via a registered interface consisting of two MMRs, namely, HVCON and HVDAT. The HVCON register acts as a command byte ...
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ADuC7032-8L High Voltage Interface Control Register Name: HVCON Address: 0xFFFF0804 Default Value: 0x00 Access: Read/write Function: This 8-bit register acts as a command byte interpreter for the high voltage control interface. Bytes written to this register are interpreted as read ...
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High Voltage Configuration 0 Register Name: HVCFG0 Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the function of high voltage circuits on the ADuC7032-8L. This register is not an ...
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ADuC7032-8L High Voltage Configuration1 Register Name: HVCFG1 Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the function of high voltage circuits on the ADuC7032-8L. This register is not an ...
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High Voltage Interrupt Status Register Name: HVSTA Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read only. This register should be read only on a high voltage interrupt. Function: This 8-bit, read-only register reflects a ...
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ADuC7032-8L High Voltage Monitor Register Name: HVMON Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read only Function: This 8-bit, read-only register reflects the current status of enabled high voltage related circuits and functions on ...
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WU (WAKE-UP) PIN The WU (wake-up) pin is a high voltage GPIO controlled via HVCON and HVDAT. WU Pin Circuit Description The WU pin is configured by default as an output with an internal 10 kΩ pull-down resistor and high-side ...
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ADuC7032-8L HANDLING INTERRUPTS FROM THE HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE An interrupt controller is also integrated with the high voltage circuits. If enabled via IRQEN[16], one of five high voltage sources can assert the high voltage interrupt (IRQ3) signal and ...
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UART SERIAL INTERFACE The ADuC7032-8L features a 16,450-compatible UART. The UART is a full-duplex universal asynchronous receiver/ transmitter that performs serial-to-parallel conversion on data characters received from a peripheral device or a modem, and parallel-to-serial conversion on data characters received ...
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ADuC7032-8L UART TX Register Name: COMTX Address: 0xFFFF0700 Default Value: 0x00 Access: Write only Function: This 8-bit register is written to when transmitting data using the UART. UART RX Register Name: COMRX Address: 0xFFFF0700 Default Value: 0x00 Access: Read only ...
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UART Control Register 1 Name: COMCON1 Address: 0xFFFF0710 Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the operation of the UART in conjunction with COMCON0. Table 82. COMCON1 MMR Bit Designations Bit Name Description UART ...
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ADuC7032-8L UART Interrupt Enable Register 0 Name: COMIEN0 Address: 0xFFFF0704 Default Value: 0x00 Access: Read/write Function: This 8-bit register enables and disables the individual UART interrupt sources. Table 84. COMIEN0 MMR Bit Designations Bit Name Description Not ...
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SERIAL PERIPHERAL INTERFACE The ADuC7032-8L features a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, that is, full duplex. The SPI ...
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ADuC7032-8L SPI Control Register Name: SPICON Address: 0xFFFF0A10 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the serial peripheral interface. Table 89. SPICON MMR Bit Designations Bit Description Reserved. Should be written ...
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SPI Status Register Name: SPISTA Address: 0xFFFF0A00 Default Value: 0x00 Access: Read only Function: This 8-bit MMR represents the current status of the serial peripheral interface. Table 90. SPISTA MMR Bit Designations Bit Description Reserved. 5 SPIRX ...
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ADuC7032-8L LIN (LOCAL INTERCONNECT NETWORK) INTERFACE LHS INTERRUPT IRQEN[7] ADuC7032-8L LHS HARDWARE 5MHz LHSVAL0 131kHz LHSVAL1 RxD ENABLE LHSCON0[8] ADuC7032-8L UART GPIO_12 GP2DAT[29] AND GP2DAT[21] GP2CON[20] The ADuC7032-8L features a high voltage physical interface between the ARM7 MCU core and ...
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LIN Hardware Synchronization Status Register Name: LHSSTA Address: 0xFFFF0780 Default Value: 0x00 Access: Read only Function: This LHS status register is an 8-bit register whose bits reflect the current operating status of the ADuC7032-8L LIN interface. Table 91. LHSSTA MMR ...
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ADuC7032-8L LIN Hardware Synchronization Control Register 0 Name: LHSCON0 Address: 0xFFFF0784 Default Value: 0x0000 Access: Read/write Function: This LHS control register is a 16-bit register that, in conjunction with the LHSCON1 register, is used to configure the LIN mode of ...
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LIN Hardware Synchronization Control Register 1 Name: LHSCON1 Address: 0xFFFF078C Default Value: 0x32 Access: Read/write Function: This LHS control register is an 8-bit register that, in conjunction with the LHSCON0 register, is used to configure the LIN mode of operation. ...
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ADuC7032-8L LIN HARDWARE INTERFACE LIN Frame Protocol The LIN frame protocol is divided into four main categories: break symbol, sync byte, protected identifier, and data bytes. The format of the frame header, break, synchronization byte, and protected identifier is shown ...
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BIT BIT > BIT BIT BIT BIT BIT STA BREAK SYNC Figure 39. LIN Interface Timing t t > 13 ...
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ADuC7032-8L Example LIN Hardware Synchronization Routine Consider the following C-source code LIN initialization routine: void LIN_INIT(void ) { char HVstatus; GP2CON = 0x110000; LHSCON0 = 0x1; do{ HVDAT = 0x02; HVCON = 0x08; do{ HVstatus = HVCON; } while(HVstatus & ...
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Example Code while((GP2DAT & 0x10 ) == LHSCON0 = 0x4; IRQEN = 0x800; LHSVAL1 BREAK LHSVAL0 STARTS RESET AND COMPARE COUNTING STARTS INTERRUPT COUNTING GENERATED T START BIT LHSVAL1 = 0x3F LIN Diagnostics The ADuC7032-8L features the ...
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ADuC7032-8L ADuC7032-8L ON-CHIP DIAGNOSTICS The ADuC7032-8L integrates multiple diagnostic support circuits on-chip. These circuits allow the device to test core digital functionality, and analog front-end and high voltage I/O ports in-circuit. ADC DIAGNOSTICS Internal Test Voltage The current channel can ...
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PART IDENTIFICATION Two registers mapped into the MMR space are intended to allow user code to identify and trace by manufacturing lot ID infor- mation , part ID number, silicon mask revision, and kernel revision. This information is contained in ...
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ADuC7032-8L System Serial ID Register 1 Name: SYSSER1 Address: 0xFFFF023C Default Value: 0x00000000 (updated by kernel at power-on) Access: Read/write Function: At power-on, this 32-bit register holds the values of the part ID number, silicon mask revision number, and kernel ...
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System Identification FEE0ADR Name: FEE0ADR Address: 0xFFFF0E10 Default Value: Nonzero Access: Read/write Function: This 16-bit register dictates the address upon which any Flash/EE command executed via FEExCON acts. Note that this MMR is also used to identify ADuC703x family members ...
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ADuC7032-8L ADuC7032-8L EXAMPLE SCHEMATIC This example schematic represents a basic functional circuit implementation. Additional components must be added to ensure the system meets any EMC and other overvoltage/overcurrent compliance requirements. ADAPTOR JTAG Figure 45. Basic Functional Circuit Implementation Rev.0 | ...
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... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 0.05 VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 ADuC7032BSTZ-8L-RL −40°C to +105°C EVAL-ADUC7032QSPZ RoHS Compliant Part. 0.75 1.60 0.60 MAX 0.45 0.20 0.09 7° 3.5° 12 0° SEATING 0.08 MAX PLANE VIEW A 0 ...
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ADuC7032-8L NOTES © 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05986-0-8/07(0) Rev.0 | Page 116 of 116 ...