ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet - Page 22

• Manufacturer Part Number: ADUC7032BSTZ-8L-RL
• Description: IC,Battery Management,QFP,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8L-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

ADuC7032-8L
Remap
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020.
By default, after a reset, the Flash/EE memory is logically mapped
to Address 0x00000000.
It is possible to logically remap the SRAM to Address 0x00000000
by setting Bit 0 of the SYSMAP0 MMR, which is located at
0xFFFF0220. To revert Flash/EE to Address 0x00000000, Bit 0 of
SYSMAP0 is cleared.
It may be desirable to remap RAM to Address 0x00000000 to
optimize the interrupt latency of the ADuC7032-8L, as code
can be run in full 32-bit ARM mode and at the maximum core
speed. It should be noted that when an exception occurs, the
core defaults to ARM mode.
Remap Operation
When a reset occurs on the ADuC7032-8L, execution starts
automatically in the factory-programmed internal configuration
code. This so-called kernel is hidden and cannot be accessed
by user code.
SYSMAP0 Register
Name: SYSMAP0
Address: 0xFFFF0220
Default Value: Updated by the kernel
Access: Read/write
Function: This 8-bit register allows user code to remap either RAM or Flash/EE space into the bottom of the ARM memory space,
starting at Address 0x00000000.
Table 11. SYSMAP0 MMR Bit Designations
Bit
7 to 1
0
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Remap Bit.
Set by the user to remap the SRAM to 0x00000000.
Cleared automatically after reset to remap the Flash/EE memory to 0x00000000.
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If the ADuC7032-8L is in normal mode, it executes the power-
on configuration routine of the kernel and then jumps to the
reset vector, Address 0x00000000, to execute the user reset
exception routine.
Because the Flash/EE is mirrored at the bottom of the memory
array at reset, the reset routine must always be written in Flash/EE.
Precautions must be taken to execute the remap command from
the absolute Flash/EE address, and not from the mirrored,
remapped segment of memory, because this segment may be
replaced by the SRAM. If a remap operation is executed while
operating code from the mirrored location, prefetch/data aborts
may occur; or the user may observe abnormal program operation.
This operation is reversible. The Flash/EE can be remapped to
Address 0x00000000 by clearing Bit 0 of the SYSMAP0 MMR.
Precautions must again be taken to execute the remap function
from outside the mirrored area.
Any kind of reset logically remaps the Flash/EE memory to the
bottom of the memory array.