ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet - Page 39
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ADUC7032BSTZ-8L-RL
Manufacturer Part Number
ADUC7032BSTZ-8L-RL
Description
IC,Battery Management,QFP,48PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7032QSPZ.pdf
(116 pages)
Specifications of ADUC7032BSTZ-8L-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
POR, PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
VOLTAGE CHANNEL ADC (V-ADC)
The V-ADC is intended to convert battery voltage. As with the
current channel ADC, described in the Current Channel ADC
(I-ADC) section, this ADC employs an identical Σ-Δ conversion
technique, including a modified Sinc3 low-pass filter to give
a valid 16-bit data conversion result at programmable output
rates from 4 Hz to 8 kHz. An external RC filter network is not
required because this is implemented internally in the voltage
channel.
The external battery voltage (VBAT) is routed to the ADC input
via an on-chip high voltage, resistive attenuator. This must be
enabled/disabled via HVCFG1[7].
The time to a first valid (fully settled) result on the voltage
channel is three ADC conversion cycles with chop mode turned
off, and two ADC conversion cycles with chop mode turned on.
This ADC is again buffered, but, unlike the current channel,
it has a fixed VBAT input range of 0 V to 28.8 V (assuming an
internal 1.2 V reference). A top level overview of this ADC
signal chain is shown in Figure 16.
*R = 60kΩ
VBAT
DIVIDE BY 24, INPUT
DIFFERENTIAL
ATTENUATOR.
ATTENUATOR
45R*
2R*
1R*
BUF
IMPEDANCE INPUT STAGE
THE BUFFER AMPLIFIERS
FOR THE ANALOG INPUT.
BUFFER AMPLIFIERS
PRESENT A HIGH
EXTERNAL REFERENCE ON
REFERENCE IS ROUTED TO
THE ADC BY DEFAULT. AN
THE VREF PIN CAN ALSO
PRECISION REFERENCE
THE INTERNAL 5ppm/°C
BE SELECTED.
CHOP
REFERENCE
PROGRAMMABLE CHOPPING
INTERNAL
ALTERNATELY REVERSED
VREF
CONVERSION CYCLE.
MODULATOR
Figure 16. Voltage ADC, Top Level Overview
THE INPUTS ARE
QUANTIZATION NOISE INTRODUCED
BY THE MODULATOR. THE UPDATE
ANALOG INPUT
FILTER ARE PROGRAMMABLE VIA
THROUGH THE
RATE AND BANDWIDTH OF THIS
Σ-Δ
THE SINC3 FILTER REMOVES
THE ADCFLT MMR.
PROGRAMMABLE
DIGITAL FILTER
Σ-Δ ADC
Rev.0 | Page 39 of 116
PROGRAMMABLE
DIGITAL FILTER
SCALED BY THE CALIBRATION
COEFFICIENTS BEFORE BEING
THE OUTPUT WORD FROM
THE DIGITAL FILTER IS
CONVERSION RESULT.
PROVIDED AS THE
OUTPUT SCALING
CYCLE OF WHICH REPRESENTS
THE DIGITAL FILTER, THE DUTY
THE MODULATOR PROVIDES A
THE SAMPLED ANALOG INPUT
HIGH FREQUENCY 1-BIT DATA
WHICH IS ALSO CHOPPED) TO
STREAM (THE OUTPUT OF
TEMPERATURE CHANNEL ADC (T-ADC)
The T-ADC is designed to convert battery temperature. The
battery temperature can be derived via the on-chip temperature
sensor or an external temperature sensor input.
The time to a first valid (fully settled) result after an input
channel switch on the temperature channel is three ADC
conversion cycles with chop mode turned off and two ADC
conversion cycles with chop mode turned on.
As with the current and voltage channel ADCs, this ADC uses
an identical Σ-Δ conversion technique, including a modified
Sinc3 low-pass filter to give a valid 16-bit data conversion result
at programmable output rates from 4 Hz to 8 kHz.
Σ-Δ MODULATOR
VOLTAGE.
COEFFICIENT
COEFFICIENT
OFFSET
GAIN
CHOP
DATA MMR
VOLTAGE
AVERAGE
OUTPUT
FORMAT
OUTPUT
RESULT
NO MISSING CODES.
ENSURES 16 BITS
ADC
ARCHITECTURE
INTERRUPT ONCE A VOLTAGE
ADC INTERRUPT GENERATOR
CONVERSION IS COMPLETE.
Σ-Δ ADC
THE Σ-Δ
INTERRUPT
GENERATES AN ADC
ADC
THE FILTER IS SUMMED AND
AS PART OF THE CHOPPING
DATA-WORD OUTPUT FROM
IMPLEMENTATION, EACH
AVERAGED WITH ITS
OUTPUT AVERAGE
PREDECESSOR.
ADuC7032-8L