ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet - Page 67

• Manufacturer Part Number: ADUC7032BSTZ-8L-RL
• Description: IC,Battery Management,QFP,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8L-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

IRQ
The IRQ is the exception signal to enter the IRQ mode of the
processor. It is used to service general-purpose interrupt
handling of internal and external events.
There are four 32-bit registers dedicated to IRQ.
IRQSIG
Reflects the status of the different IRQ sources. If a peripheral
generates an IRQ signal, the corresponding bit in the IRQSIG is
set; otherwise, it is cleared. The IRQSIG bits are cleared when the
interrupt in the particular peripheral is cleared. All IRQ sources
can be masked in the IRQEN MMR. IRQSIG is read only and can
be used to poll interrupt sources.
IRQEN
Provides the value of the current enable mask. When the bit is
set to 1, the source request is enabled to create an IRQ exception.
When the bit is set to 0, the source request is disabled or masked
and does not create an IRQ exception.
IRQCLR
A write-only register that allows clearing the IRQEN register to
mask an interrupt source. Each bit set to 1 clears the corresponding
bit in the IRQEN register without affecting the remaining bits.
The pair of registers, IRQEN and IRQCLR, allow independent
manipulation of the enable mask without requiring an auto-
matic read-modify-write.
IRQSTA
A read-only register that provides the current enabled IRQ source
status (effectively a Logic AND of the IRQSIG and IRQEN bits).
When the bit is set to 1, that source generates an active IRQ request
to the ARM7TDMI core. There is no priority encoder or interrupt
vector generation. This function is implemented in software in a
common interrupt handler routine. All 32 bits are logically OR’ e d
to create a single IRQ signal to the ARM7TDMI core.
FIQ
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface, providing the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ, FIQSIG, FIQEN, FIQCLR, and FIQSTA.
Bit 31 to Bit 1 of FIQSTA are logically OR’ e d to create the FIQ
signal to the core and to Bit 0 of both the FIQ and IRQ registers
(FIQ source).
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The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to 1
in FIQEN, as a side effect, clears the same bit in IRQEN.
A bit set to 1 in IRQEN, as a side effect, clears the same bit in
FIQEN. An interrupt source can be disabled in both IRQEN
and FIQEN masks.
Programmed Interrupts
Because the programmed interrupts are nonmaskable, they are
controlled by another register, SWICFG, which writes into both
IRQSTA and IRQSIG registers and/or FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG,
described in Table 52. This MMR allows the control of
programmed source interrupt.
Table 52. SWICFG MMR Bit Designations
Bit
31 to 3
2
1
0
Note that to be detected by the interrupt controller and to be
detected by the user in the IRQSTA and FIQSTA registers, any
interrupt signal must be active for at least the minimum
interrupt latency time.
FLASH/EE
PLL LOCK
FLASH/EE
PLL LOCK
Description
Reserved.
Programmed Interrupt FIQ.
Setting/clearing this bit corresponds to
setting/clearing Bit 1 of FIQSTA and FIQSIG.
Programmed Interrupt IRQ.
Setting/clearing this bit corresponds to
setting/clearing Bit 1 of IRQSTA and IRQSIG.
Reserved.
LIN H/W
LIN H/W
TIMER0
TIMER1
TIMER2
TIMER3
TIMER0
TIMER1
TIMER2
TIMER3
UART
UART
XIRQ
XIRQ
ADC
ADC
SPI
SPI
Figure 29. Interrupt Structure
ADuC7032-8L
IRQ
FIQ