ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet - Page 20

• Manufacturer Part Number: ADUC7032BSTZ-8L-RL
• Description: IC,Battery Management,QFP,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8L-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

1
ADuC7032-8L
EmbeddedICE (I)
The EmbeddedICE module provides integrated on-chip debug
support for the ARM7TDMI. The EmbeddedICE module contains
the breakpoint and watchpoint registers, which allow nonintrusive
user code debugging. These registers are controlled through the
JTAG test port.
When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. Once in a debug state, the processor
registers may be interrogated, as well as the Flash/EE, the SRAM,
and the memory mapped registers.
ARM7 Exceptions
The ARM7 supports five types of exceptions, with a privileged
processing mode associated with each type. The five types of
exceptions follow:
•
•
•
•
•
Typically, the programmer defines interrupts as IRQ; but for
higher priority interrupts, the programmer can define interrupts
as being of the FIQ type.
The priority of the above exceptions and vector addresses are
shown in Table 10.
Table 10. Exception Priority
Priority
1
2
3
4
5
6
6
priority and are mutually exclusive.
The exceptions in Table 10 are located from Address 0x00 to
Address 0x1C, with a reserved location at 0x14. This location is
required to be written with either 0x27011970 or the checksum
of Page 0, excluding Location 0x14. If this is not done, user code
is not executed, and LIN download mode is entered.
A software interrupt and an undefined instruction exception have the same
Normal interrupt or IRQ. It is provided to service general-
purpose interrupt handling of internal and external events.
Fast interrupt or FIQ. It is provided to service data transfer or
a communication channel with low latency. FIQ has priority
over IRQ.
Memory abort (prefetch and data).
Attempted execution of an undefined instruction.
Software interrupt (SWI) instruction. It can be used to
make a call to an operating system.
Exception
Hardware reset
Memory abort (data)
FIQ
IRQ
Memory abort (prefetch)
Software interrupt
Undefined instruction
1
1
Vector Address
0x00
0x10
0x1C
0x18
0x0C
0x04
0x04
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ARM Registers
The ARM7TDMI has 16 standard registers. R0 to R12 are used
for data manipulation, R13 is the stack pointer, R14 is the link
register, and R15 is the program counter that indicates the
instruction currently being executed. The link register contains
the address from which the user has branched, if the branch and
link command was used, or the command during which an
exception occurred.
The stack pointer (R13) contains the current location of the stack.
Typically on an ARM7TDMI, the stack starts at the top of the
available RAM area and descends, using the area as required.
A separate stack is defined for each exception. The size of each
stack is user configurable and is dependent on the target
application. On the ADuC7032-8L, the stack begins at
0x000417FC and descends.
When programming using a high level language such as C, it is
necessary to ensure that the stack does not overflow. This is
dependent on the performance of the compiler that is used.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14), as represented
in Figure 9. The FIQ mode has more registers (R8 to R12),
supporting faster interrupt processing. With the increased
number of noncritical registers, the interrupt can be processed
without the need to save or restore these registers, reducing the
response time of the interrupt handling process.
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly from
ARM Ltd.
USER MODE
R15 (PC)
CPSR
R10
R11
R12
R13
R14
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
SPSR_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R8_FIQ
R9_FIQ
Figure 9. Register Organization
MODE
FIQ
SPSR_SVC
R13_SVC
R14_SVC
MODE
SVC
SPSR_ABT
R13_ABT
R14_ABT
ABORT
MODE
USABLE IN USER MODE
SYSTEM MODES ONLY
SPSR_IRQ
R13_IRQ
R14_IRQ
MODE
IRQ
UNDEFINED
SPSR_UND
R13_UND
R14_UND
MODE