ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet - Page 99

• Manufacturer Part Number: ADUC7032BSTZ-8L-RL
• Description: IC,Battery Management,QFP,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8L-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

SERIAL PERIPHERAL INTERFACE
The ADuC7032-8L features a complete hardware serial
peripheral interface (SPI) on-chip. SPI is an industry-standard
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and received simultaneously, that is,
full duplex.
The SPI is operational only with core clock divider bits
(POWCON[2:0] = 0 or 1).
The SPI port can be configured for master or slave operation
and consists of four pins that are multiplexed with four GPIOs.
The four SPI pins are MISO, MOSI, SCLK, and SS . The pins to
which these signals are connected are shown in Table 87.
Table 87. SPI Output Pins
Pin
GPIO_0 (GPIO MODE 1)
GPIO_1 (GPIO MODE 1)
GPIO_2 (GPIO MODE 1)
GPIO_3 (GPIO MODE 1)
MISO (MASTER IN, SLAVE OUT DATA I/O PIN)
The MISO (master in, slave out) pin is configured as an input
line in master mode and an output line in slave mode. The
MISO line on the master (data in) should be connected to the
MISO line in the slave device (data out). The data is transferred
as byte wide (8-bit) serial data, MSB first.
MOSI (MASTER OUT, SLAVE IN PIN)
The MOSI (master out, slave in) pin is configured as an output
line in master mode and an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte
wide (8-bit) serial data, MSB first.
SCLK (SERIAL CLOCK I/O PIN)
The master serial clock (SCLK) is used to synchronize the data
being transmitted and received through the MOSI SCLK period.
Therefore, a byte is transmitted/received after eight SCLK
periods. The SCLK pin is configured as an output in master
mode and as an input in slave mode.
SCLK
MOSI
Signal
SS
MISO
Serial Clock
Master Out, Slave In
Description
Chip Select
Master In, Slave Out
Rev.0 | Page 99 of 116
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
The maximum speed of the SPI clock is dependent on the clock
divider bits and is summarized in Table 88.
Table 88. SPI Speed vs. Clock Divider Bits in Master Mode
CD Bits
SPIDIV
Maximum SCLK
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 5.12 Mb at CD = 0.
The formula to determine the maximum speed follows:
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is impor-
tant that the polarity and phase be configured in the same way
for the master and slave devices.
CHIP SELECT (SS) INPUT PIN
In SPI slave mode, a transfer is initiated by the assertion of SS ,
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by
deassertion of SS . In slave mode, SS is always an input.
SPI REGISTERS DEFINITIONS
The following MMR registers are used to control the SPI interface:
•
•
•
•
•
SPICON: 16-bit control register
SPISTA: 8-bit read-only status register
SPIDIV: 8-bit serial clock divider register
SPIRX: 8-bit read-only receive register
SPITX: 8-bit write-only transmit register
f
f
SERIALCLOC
SERIALCLOC
K
K
=
2
=
×
20
f
1 (
HCLK
.
4
+
48
SPIDIV
0
0x05
1.667 MHz
MHz
)
ADuC7032-8L
0x0B
1
0.833 MHz