ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet - Page 103

• Manufacturer Part Number: ADUC7032BSTZ-8L-RL
• Description: IC,Battery Management,QFP,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8L-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

LIN Hardware Synchronization Status Register
Name: LHSSTA
Address: 0xFFFF0780
Default Value: 0x00
Access: Read only
Function: This LHS status register is an 8-bit register whose bits reflect the current operating status of the ADuC7032-8L LIN interface.
Table 91. LHSSTA MMR Bit Designations
Bit
7 to 6
5
4
3
2
1
0
Description
Reserved. These read-only bits are reserved for future use.
LHS Reset Complete Flag.
Break Field Error.
LHS Compare Interrupt.
Stop Condition Interrupt.
Start Condition Interrupt.
Break Timer Compare Interrupt.
Set to 1 by hardware to indicate an LHS reset command has completed successfully.
Cleared to 0 after user code reads the LHSSTA MMR.
Set to 1 by hardware and generates an LHS interrupt (IRQEN[7]) when the 12-bit break timer (LHSVAL1) register overflows to
indicate the LIN bus has stayed low too long, thus indicating a possible LIN bus error.
Cleared to 0 after user code reads the LHSSTA MMR.
Set to 1 by hardware when the value in LHSVAL0 (LIN synchronization bit timer) = the value in the LHSCMP register.
Cleared to 0 after user code reads the LHSSTA MMR.
Set to 1 by hardware when a stop condition is detected.
Cleared to 0 after user code reads LHSSTA MMR.
Set to 1 by hardware when a start condition is detected.
Cleared to 0 after user code reads LHSSTA MMR.
Set to 1 by hardware when a valid LIN break condition is detected. A LIN break condition is generated when the LIN break timer
value reaches the break timer compare value (see the LHSVAL1 description in the LIN Hardware Break Timer1 Register section).
Cleared to 0 after user code reads the LHSSTA MMR.
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ADuC7032-8L