ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet - Page 66

• Manufacturer Part Number: ADUC7032BSTZ-8L-RL
• Description: IC,Battery Management,QFP,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8L-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

ADuC7032-8L
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 16 interrupt sources on the ADuC7032-8L that are
controlled by the interrupt controller. Most interrupts are
generated from the on-chip peripherals such as the ADC,
UART, and so on. The ARM7TDMI CPU core recognizes
interrupts as only one of two types: a normal interrupt request
(IRQ) and a fast interrupt request (FIQ). All the interrupts can
be masked separately.
The control and configuration of the interrupt system are
managed through nine interrupt-related registers, four
dedicated to IRQ and four dedicated to FIQ. An additional
MMR is used to select the programmed interrupt source. The
bits in each IRQ and FIQ register represent the same interrupt
source, as shown in Table 51.
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid
interrupt sources are serviced.
The interrupt generation route through the ARM7TDMI core is
shown in Figure 29.
Table 51. IRQ/FIQ MMRs Bit Designations
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Description
All interrupts OR’ed (FIQ only).
SWI is not used in IRQEN/CLR and FIQEN/CLR.
Timer0.
Timer1.
Timer2 or Wake-Up Timer.
Timer3 or Watchdog Timer.
Reserved. Should be written as 0.
LIN Hardware.
Flash/EE Interrupt.
PLL Lock.
ADC.
UART.
SPI Master.
XIRQ0 (GPIO IRQ 0).
XIRQ1 (GPIO IRQ 1).
Reserved. Should be written as 0.
IRQ3. High voltage IRQ.
SPI Slave.
XIRQ4 (GPIO IRQ 4).
XIRQ5 (GPIO IRQ 5).
Comments
See the Timer0—Lifetime Timer section.
See the Timer1 section.
See the Timer2—Wake-Up Timer section.
See the Timer3—Watchdog Timer section.
See the LIN (Local Interconnect Network) Interface section
See the Flash/EE Control Interface section.
See the ADUC7032-8L System Clocks section.
See the 16-Bit, Sigma-Delta Analog-to-Digital Converters section.
See the UART Serial Interface section.
See the Serial Peripheral Interface section.
See the General-Purpose I/O section.
See the General-Purpose I/O section.
High voltage interrupt; see the High Voltage Peripheral Control Interface section
See the General-Purpose I/O section.
See the General-Purpose I/O section.
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Consider the example of Timer0, which is configured to
generate a timeout every 1 ms. After the first 1 ms timeout,
FIQSIG/IRQSIG[2] is set and can be cleared only by writing to
T0CLRI.
If Timer0 is not enabled in either IRQEN or FIQEN,
FIQSTA/IRQSTA[2] is not set and an interrupt does not occur.
If Timer0 is enabled in either IRQEN or FIQEN, then
FIQSTA/IRQSTA[2] is set and either an FIQ or an IRQ
interrupt occurs.
Note that the IRQ and FIQ interrupt bit definitions in the CPSR
control interrupt recognition by the ARM core only, not by the
peripherals. For example, if Timer2 is configured to generate an
IRQ via IRQEN, the IRQ interrupt bit is set (disabled) in the
CPSR, and the ADuC7032-8L is powered down. When an
interrupt occurs, the peripherals power up, but the ARM core
remains powered down. This is equivalent to POWCON =
0x71. The ARM core can be powered up only by a reset event if
this occurs.