ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet - Page 101

• Manufacturer Part Number: ADUC7032BSTZ-8L-RL
• Description: IC,Battery Management,QFP,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8L-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

SPI Status Register
Name: SPISTA
Address: 0xFFFF0A00
Default Value: 0x00
Access: Read only
Function: This 8-bit MMR represents the current status of the serial peripheral interface.
Table 90. SPISTA MMR Bit Designations
Bit
7 to 6
5
4
3
2
1
0
SPI Divider Register
Name: SPIDIV
Address: 0xFFFF0A0C
Default Value: 0x1B
Access: Read/write
Function: This 8-bit MMR represents the frequency at which the serial peripheral interface is operating. For more information on the
calculation of the baud rate, see the SCLK (Serial Clock I/O Pin) section.
SPI Receive Register
Name: SPIRX
Address: 0xFFFF0A04
Default Value: 0x00
Access: Read only
Function: This 8-bit MMR contains the data received via the serial peripheral interface.
SPI Transmit Register
Name: SPITX
Address: 0xFFFF0A08
Default Value: 0x00
Access: Write only
Function: This 8-bit MMR is written to, to transmit data via the serial peripheral interface.
Description
Reserved.
SPIRX Data Register Overflow Status Bit.
SPIRX Data Register IRQ.
SPIRX Data Register Full Status Bit.
SPITX Data Register Underflow Status Bit.
SPITX Data Register IRQ.
SPITX Data Register Empty Status Bit.
Set if SPIRX is overflowing.
Cleared by reading SPIRX register.
Set automatically if Bit 3 or Bit 5 is set.
Cleared by reading SPIRX register.
Set automatically if valid data is present in the SPIRX register.
Cleared by reading SPIRX register.
Set automatically if SPITX is underflowing.
Cleared by writing in the SPITX register.
Set automatically if Bit 0 is cleared or Bit 2 is set.
Cleared by writing in the SPITX register or, if transmission finished, by disabling the SPI.
Set by writing to SPITX to send data. This bit is set during transmission of data.
Cleared when SPITX is empty.
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ADuC7032-8L