ADUC7032BSTZ-8L-RL Analog Devices Inc, ADUC7032BSTZ-8L-RL Datasheet - Page 23

• Manufacturer Part Number: ADUC7032BSTZ-8L-RL
• Description: IC,Battery Management,QFP,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7032BSTZ-8L-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

1
2
RAM is valid except in the case of a reset following a LIN download.
The impact of RAM is dependent on the contents of HVSTA[6] if LVF is enabled. When LVF is enabled using (HVCFG0[2]), RAM has not been corrupted by the POR reset
RESET
There are four kinds of reset: external reset, power-on reset,
watchdog reset, and software reset. The RSTSTA register indicates
the source of the last reset and can also be written by user code
to initiate a software reset event. The bits in this register can be
cleared to 0 by writing to the RSTCLR MMR at 0xFFFF0234.
Table 12. Device Reset Implications
Impact/Reset
POR
Watchdog Reset
Software Reset
External Reset Pin
mechanism if the LVF Status Bit HVSTA[6] = 1. See the Low Voltage Flag (LVF) section for more information.
RSTCLR Register
Name: RSTCLR
Address: 0xFFFF0234
Default Value: 0x00
Access: Write only
Function: This 8-bit write-only register clears the corresponding bit in RSTSTA.
RSTSTA Register
Name: RSTSTA
Address: 0xFFFF0230
Default Value: 0x01
Access: Read/write
Function: This 8-bit register indicates the source of the last reset event and can also be written by user code to initiate
a software reset.
Table 13. RSTCLR/RSTSTA MMR Bit Designations
Bit
7 to 4
3
2
1
0
1
If the software reset bit in RSTSTA is set, any write to RSTCLR that does not clear this bit generates a software reset.
1
Description
Not Used. These bits are not used and always read as 0.
External Reset.
Software Reset.
Watchdog Timeout.
Power-On Reset.
Reset External Pins
to Default State
Yes
Yes
Yes
Yes
Set to 1 automatically when an external reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
Set to 1 by user code to generate a software reset.
Cleared by setting the corresponding bit in RSTCLR.
Set to 1 automatically when a watchdog timeout occurs.
Cleared by setting the corresponding bit in RSTCLR.
Set automatically when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
1
Kernel
Executed
Yes
Yes
Yes
Yes
Reset All
External MMRs
(Excluding RSTSTA)
Yes
Yes
Yes
Yes
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The bit designations in RSTCLR mirror those of RSTSTA.
These registers can be used during a reset exception service
routine to identify the source of the reset. The implications of
all four kinds of reset event are listed in Table 12.
Reset All
High Voltage
Indirect
Registers
Yes
Yes
Yes
Yes
Peripherals
Reset
Yes
Yes
Yes
Yes
RAM
Valid
Yes/No
Yes
Yes
Yes
1
2
ADuC7032-8L
RSTSTA
(Status After
Reset Event)
RSTSTA[0] = 1
RSTSTA[1] = 1
RSTSTA[2] = 1
RSTSTA[3] = 1