AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 123

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

been selected). Then a second access is performed,
this time to the RDP offset of 10h (for either WIO or
DWIO mode). The RDP access is a read access, and
since RAP has just been loaded with the value of 0004h,
the RDP read will yield the contents of CSR4. A read of
the BDP at this time (offset of 16h when WIO mode has
been selected, 1Ch when DWIO mode has been select-
ed) will yield the contents of BCR4, since the RAP is
used as the pointer into both BDP and RDP space.
RAP: Register Address Port
Bit
31-16
15-8
7-0
Control and Status Registers
The CSR space is accessible by performing accesses
to the RDP (Register Data Port). The particular CSR
that is read or written during an RDP access will depend
upon the current setting of the RAP. RAP serves as a
pointer into the CSR space.
CSR0: Am79C973/Am79C975 Controller Status and
Control Register
Certain bits in CSR0 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR0 and write back
the value just read to clear the interrupt condition.
Bit
31-16
Name
RES
RES
RAP
Name
RES
zeros and read as undefined.
written as zeros.
of these 8 bits determines which
CSR or BCR will be accessed
when an I/O access to the RDP
or BDP port, respectively, is per-
formed.
A write access to undefined CSR
or BCR locations may cause un-
expected reprogramming of the
Am79C973/Am79C975
registers. A read access will yield
undefined values.
Read/Write accessible always.
RAP is cleared by H_RESET or
S_RESET and is unaffected by
setting the STOP bit.
zeros and read as undefined.
Description
Reserved locations. Written as
Reserved locations. Read and
Register Address Port. The value
Description
Reserved locations. Written as
P R E L I M I N A R Y
Am79C973/Am79C975
control
15
14
13
12
ERR
RES
CERR
MISS
Read accessible always. ERR is
read only. Write operations are
ignored.
When the MII port is selected,
CERR is only reported when the
external PHY is operating as a
half-duplex 10BASE-T PHY.
CERR assertion will not result in
an interrupt being generated.
CERR assertion will set the ERR
bit.
Read/Write accessible always.
CERR is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
When MISS is set, INTA is as-
serted if IENA is 1 and the mask
Error is set by the OR of CERR,
MISS, and MERR. ERR remains
set as long as any of the error
flags are true.
Reserved locations. Read/Write
accessible always. Read returns
zero.
Collision Error is set by the
Am79C973/Am79C975 controller
when the device operates in half-
duplex mode and the collision in-
puts (10 Mbps) failed to activate
within 20 network bit times after
the chip terminated transmission
(SQE Test). This feature is a
10BASE-T PHY test feature.
CERR reporting is disabled when
the Am79C973/Am79C975 con-
troller operates in full-duplex
mode.
Missed Frame is set by the
Am79C973/Am79C975 controller
when it has lost an incoming re-
ceive frame resulting from a Re-
ceive
available. This bit is the only im-
mediate indication that receive
data has been lost since there is
no current receive descriptor.
The
(CSR112) also increments each
time a receive frame is missed.
Missed
CERR
Descriptor
Frame
is
cleared
not
Counter
being
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by