AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 185

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

BCR32: PHY Control and Status Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15
14
ANTST
MIIPD
Name
Reserved locations. Written as
zeros and read as undefined.
Reserved
tests. Written as 0 and read as
undefined.
MII PHY Detect. MIIPD reflects
the quiescent state of the MDIO
pin. MIIPD is continuously updat-
ed whenever there is no manage-
ment operation in progress on the
MII interface. When a manage-
ment operation begins on the in-
terface, the state of MIIPD is
preserved until the operation
ends, when the quiescent state is
again monitored and continuous-
ly updates the MIIPD bit. When
the MDIO pin is at a quiescent
LOW state, MIIPD is cleared to 0.
When the MDIO pin is at a quies-
cent HIGH state, MIIPD is set to
1. MIIPD is used by the automatic
port selection logic to select the
MII port. When the MIIPD bit is
set to 1, the MII port is selected.
Any transition on the MIIPD bit
The STVAL value is interpreted
as an unsigned number with a
resolution of 256 Time Base
Clock periods. For instance, a
value of 122 ms would be pro-
grammed with a value of 9531
(253Bh) if the Time Base Clock is
running at 20 MHz. A value of 0 is
undefined and will result in erratic
behavior.
Read and write accessible al-
ways. STVAL is set to FFFFh af-
ter H_RESET and is unaffected
by S_RESET and the STOP bit.
Note: Use of this bit will cause
data corruption and erroneous
operation.
Read/Write accessible always.
ANTST is set to 0 by H_RESET
and is unaffected by S_RESET
and the STOP bit.
Description
for
manufacturing
P R E L I M I N A R Y
Am79C973/Am79C975
13-12 FMDC
11
FMDC
00
01
10
11
APEP
Table 37. FMDC Values
Fast Management Data Clock
Fast Management Data Clock (is
will set the MIIPDTI bit in CSR7,
bit 3.
Read accessible always. MIIPD
is read only. Write operations are
ignored and should not be per-
formed.
used for manufacturing tests).
When FMDC is set to 2h the MII
Management Data Clock will run
at 10 MHz max. The Manage-
ment Data Clock will no longer be
IEEE 802.3u-compliant and set-
ting this bit should be used with
care. The accompanying external
PHY must also be able to accept
management frames at the new
clock rate. When FMDC is set to
1h, the MII Management Data
Clock will run at 5 MHz max. The
Management Data Clock will no
longer be IEEE 802.3u-compliant
and setting this bit should be
used with care. The accompany-
ing external PHY must also be
able
frames at the new clock rate.
When FMDC is set to 0h, the MII
Management Data Clock will run
at 2.5 MHz max and will be fully
compliant to IEEE 802.3u stan-
dards. See Table 37.
Read/Write accessible always.
FMDC
H_RESET, and is unaffected by
S_RESET and the STOP bit
Auto-Poll PHY. APEP when set to
1
controller will poll the status regis-
ter in the PHY. This feature al-
lows the software driver or upper
layers to see any changes in the
status of the PHY. An interrupt
when enabled is generated when
the contents of the new status is
different from the previous status.
the
to
2.5 MHz max
10 MHz max
5 MHz max
Reserved
is
Am79C973/Am79C975
accept
set
to
management
0
during
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