AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 134

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

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RXFRTG
RDMD
and the Am79C973/Am79C975
controller will completely receive
a receive packet if it had already
begun. Additionally, all transmit
packets stored in the transmit
FIFOs and the transmit buffer
area in the SRAM (if one is en-
abled) will be transmitted and all
receive packets stored in the re-
ceive FIFOs, and the receive
buffer area in the SRAM (if one is
enabled) will be transferred into
system memory. Since the FIFO
and SRAM contents are flushed,
it may take much longer before
the Am79C973/Am79C975 con-
troller enters the suspend mode.
The amount of time that it takes
depends on many factors includ-
ing the size of the SRAM, bus la-
tency, and network traffic level.
When a write to CSR5 is per-
formed with bit 0 (SPND) set to 1,
the value that is simultaneously
written to FASTSPNDE is used to
determine which approach is
used to enter suspend mode.
Read/Write accessible always.
FASTSPNDE
H_RESET, S_RESET or by set-
ting the STOP bit.
ceive Frame Tag is set to 1, a tag
word is put into the receive de-
scriptor supplied by the EADI.
See the section Receive Frame
Tagging for details. This bit is
valid only when the EADISEL
(BCR2, bit 3) is set to 1.
Read/Write accessible always.
RXFRTG
H_RESET. RXFRTG is unaffect-
ed by S_RESET or by setting the
STOP bit.
causes the Buffer Management
Unit to access the Receive De-
scriptor Ring without waiting for
the receive poll-time counter to
elapse. If RXON is not enabled,
RDMD has no meaning and no
receive Descriptor Ring access
will occur.
Receive Frame Tag. When Re-
Receive Demand, when set,
is
is
cleared
cleared
P R E L I M I N A R Y
Am79C973/Am79C975
by
by
12
11
RXDPOLL
STINT
RDMD is required to be set if the
RXDPOLL bit in CSR7 is set. Set-
ting RDMD while RXDPOLL = 0
merely hastens the Am79C973/
Am79C975 controller’s response
to a receive Descriptor Ring En-
try.
Read/Write accessible always.
RDMD is set by writing a 1. Writ-
ing a 0 has no effect. RDMD will
be cleared by the Buffer Manage-
ment Unit when it fetches a re-
ceive
cleared by H_RESET. RDMD is
unaffected by S_RESET or by
setting the STOP bit.
Read/Write accessible always.
RXDPOLL
H_RESET. RXDPOLL is unaf-
fected by S_RESET or by setting
the STOP bit.
When STINT is set to 1, INTA is
asserted if the enable bit STINTE
is set to 1.
Read/Write accessible always.
STINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Receive Disable Polling. If RXD-
POLL is set, the Buffer Manage-
ment Unit will disable receive
polling. Likewise, if RXDPOLL is
cleared, automatic receive poll-
ing is enabled. If RXDPOLL is
set, RDMD bit in CSR7 must be
set in order to initiate a manual
poll of a receive descriptor. Re-
ceive Descriptor Polling will not
take place if RXON is reset.
Software Timer interrupt is set by
the Am79C973/Am79C975 con-
troller when the Software Timer
counts down to 0. The Software
Timer will immediately load the
STVAL (BCR 31, bits 5-0) into the
Software Timer and begin count-
ing down.
Software Timer Interrupt. The
STINT
Descriptor.
is
is
cleared
cleared
RDMD
by
by
is