AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 31

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

REQ
Bus Request
The Am79C973/Am79C975 controller asserts REQ pin
as a signal that it wishes to become a bus master. REQ
is driven high when the Am79C973/Am79C975 control-
ler does not request the bus. In Power Management
mode, the REQ pin will not be driven.
When RST is active, REQ is an input for NAND tree
testing.
RST
Reset
When RST is asserted LOW and the PG pin is HIGH,
then the Am79C973/Am79C975 controller performs an
i n t e r n a l s y s t e m r e s e t o f t h e t y p e H _ R E S E T
(HARDWARE_RESET, see section on RESET). RST
must be held for a minimum of 30 clock periods. While
in the H_RESET state, the Am79C973/Am79C975
controller will disable or deassert all outputs. RST may
be asynchronous to clock when asserted or deas-
serted.
When the PG pin is LOW, RST disables all of the PCI
pins except the PME pin.
When RST is LOW and PG is HIGH, NAND tree testing
is enabled.
SERR
System Error
Dur ing any slave transaction, the Am79C973/
Am79C975 controller asserts SERR when it detects an
address parity error, and reporting of the error is en-
abled by setting PERREN (PCI Command register, bit
6) and SERREN (PCI Command register, bit 8) to 1.
By default SERR is an open-drain output. For compo-
nent test, it can be programmed to be an active-high
totem-pole output.
When RST is active, SERR is an input for NAND tree
testing.
STOP
Stop
In slave mode, the Am79C973/Am79C975 controller
drives the STOP signal to inform the bus master to stop
the current transaction. In bus master mode, the
Am79C973/Am79C975 controller checks STOP to de-
termine if the target wants to disconnect the current
transaction.
When RST is active, STOP is an input for NAND tree
testing.
Input/Output
Input/Output
P R E L I M I N A R Y
Am79C973/Am79C975
Output
Input
TRDY
Target Ready
TRDY indicates the ability of the target of the transac-
tion to complete the current data phase. Wait states are
inserted until both IRDY and TRDY are asserted simul-
taneously. A data phase is completed on any clock
when both IRDY and TRDY are asserted.
When the Am79C973/Am79C975 controller is a bus
master, it checks TRDY during all read data phases to
determine if valid data is present on AD[31:0]. During
all write data phases, the device checks TRDY to deter-
mine if the target is ready to accept the data.
When the Am79C973/Am79C975 controller is the tar-
get of a transaction, it asserts TRDY during all read
data phases to indicate that valid data is present on
AD[31:0]. During all write data phases, the device as-
serts TRDY to indicate that it is ready to accept the
data.
When RST is active, TRDY is an input for NAND tree
testing.
PME
Power Management Event
PME is an output that can be used to indicate that a
power management event (a Magic Packet, an OnNow
pattern match, or a change in link state) has been de-
tected. The PME pin is asserted when either
1. PME_STATUS and PME_EN are both 1, or
2. PME_EN_OVR and MPMAT are both 1, or
3. PME_EN_OVR and LCDET are both 1.
The PME signal is asynchronous with respect to the
PCI clock.
VAUXDET
Auxiliary Power Detect
VAUXDET is used to sense the presence of the auxil-
iary power and correctly report the capability of assert-
ing PME signal in D3 cold. The VAUXDET pin should
be connected to the auxiliary power supply or to ground
through a resistor. If PCI power is used to power the de-
vice, a pull-down resistor is required. For systems that
provide auxiliary power, the VAUXDET pin should be
tied to auxiliary power through a pull-up resistor.
Board Interface
Note: Before programming the LED pins, see the
description of LEDPE in BCR2, bit 12.
LED0
LED0
This output is designed to directly drive an LED. By de-
fault, LED0 indicates an active link connection. This pin
can also be programmed to indicate other network sta-
Output, Open Drain
Input/Output
Output
Input
31