AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 151

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

9-8
XMTSP[1:0]
Table 27. Transmit Start Point Programming
00
01
10
00
01
10
11
11
XMTFW[1:0] Transmit FIFO Watermark. XMT-
SRAM_SIZE
ted, because no collision han-
dling is required in these modes.
When
SRAM_SIZE > 0, there is a re-
striction that the number of bytes
written is a combination of bytes
written into the Bus Transmit
FIFO and the MAC Transmit
FIFO.
Am79C975 controller supports a
mode that will wait until a full
packet is available before com-
mencing with the transmission of
preamble. This mode is useful in
a system where high latencies
cannot be avoided. See Table 27.
FW specifies the point at which
transmit
based upon the number of bytes
that could be written to the Trans-
mit FIFO without FIFO overflow.
Transmit DMA is requested at
Note that when the SRAM is be-
ing used, if the NOUFLO bit
(CSR80, bit 14) is set to 1, there
is the additional restriction that
the complete transmit frame must
be DMA’d into the Am79C973/
Am79C975 controller and reside
within a combination of the Bus
Transmit FIFO, the SRAM, and
the MAC Transmit FIFO.
Read/Write accessible only when
either the STOP or the SPND bit
is set. XMTSP is set to a value of
01b (64 bytes) after H_RESET or
S_RESET and is unaffected by
STOP.
>0
>0
>0
>0
0
0
0
0
the
DMA
The
NOUFLO bit is set
Full Packet when
SRAM
Bytes Written
220 max
is
128
128
20
64
36
64
Am79C973/
P R E L I M I N A R Y
requested,
is
Am79C973/Am79C975
used,
7-0
Table 28. Transmit Watermark Programming
XMTFW[1:0]
DMATC[7:0] DMA Transfer Counter. Writing
00
01
10
11
any time when the number of
bytes specified by XMTFW could
be written to the FIFO without
causing Transmit FIFO overflow,
and the internal microcode en-
gine has reached a point where
the Transmit FIFO is checked to
determine if DMA servicing is re-
quired.
When operating in the NO-SRAM
mode
SRAM_SIZE set to 0, the Bus
Transmit FIFO and the MAC
Transmit FIFO operate like a sin-
gle FIFO and the watermark val-
ue selected by XMTFW[1:0] sets
the number of FIFO byte loca-
tions that must be available in the
FIFO before receive DMA is re-
quested.
When operating with the SRAM,
the Bus Transmit FIFO and the
MAC Transmit FIFO operate in-
dependently on the bus side and
MAC side of the SRAM, respec-
tively. In this case, the watermark
value set by XMTFW[1:0] sets the
number of FIFO byte locations
that must be available in the Bus
Transmit FIFO. See Table 28.
Read/Write accessible only when
either the STOP or the SPND bit
is set. XMTFW is set to a value of
00b (16 bytes) after H_RESET or
S_RESET and is unaffected by
STOP.
and reading to this field has no ef-
fect.
MIN_GNT in the PCI configura-
tion space.
Use
(no
Bytes Available
SRAM
Reserved
MAX_LAT
108
16
64
enabled),
151
and