AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 66

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

Note: The value of CSR2, bits 15-8, is used as the
upper 8-bits for all memory addresses during bus mas-
ter transfers.
Figure 32 illustrates the relationship between the initial-
ization base address, the initialization block, the re-
ceive and transmit descriptor ring base addresses, the
receive and transmit descriptors, and the receive and
transmit data buffers, when SSIZE32 is set to 1.
Polling
If there is no network channel activity and there is no
pre- or post-receive or pre- or post-transmit activity
being performed by the Am79C973/Am79C975 con-
troller, then the Am79C973/Am79C975 controller will
periodically poll the current receive and transmit de-
scriptor entries in order to ascertain their ownership. If
the DPOLL bit in CSR4 is set, then the transmit polling
function is disabled.
A typical polling operation consists of the following se-
quence. The Am79C973/Am79C975 controller will use
the current receive descriptor address stored internally
66
RLE
TLE
IADR[31:16]
CSR2
Initialization
LADRF[47:32]
LADRF[63:48]
LADRF[31:16]
RES
RES
LADRF[15:0]
PADR[31:16]
PADR[47:32]
RDRA[15:0]
PADR[15:0]
TDRA[15:0]
Block
MOD
TDRA[23:16]
RDRA[23:16]
IADR[15:0]
CSR1
Figure 31. 16-Bit Software Model
P R E L I M I N A R Y
Am79C973/Am79C975
Buffers
Buffers
Rcv
Xmt
1st desc.
start
to vector to the appropriate Receive Descriptor Table
Entry (RDTE). It will then use the current transmit de-
scriptor address (stored internally) to vector to the ap-
propriate Transmit Descriptor Table Entry (TDTE). The
accesses will be made in the following order: RMD1,
then RMD0 of the current RDTE during one bus arbitra-
tion, and after that, TMD1, then TMD0 of the current
TDTE during a second bus arbitration. All information
collected during polling activity will be stored internally
in the appropriate CSRs, if the OWN bit is set (i.e.,
CSR18, CSR19, CSR20, CSR21, CSR40, CSR42,
CSR50, CSR52).
A typical receive poll is the product of the following con-
ditions:
1. Am79C973/Am79C975 controller does not own the
2. Am79C973/Am79C975 controller does not own the
1st desc.
start
RMD
TMD
Buffer
current RDTE and the poll time has elapsed and
RXON = 1 (CSR0, bit 5), or
next RDTE and there is more than one receive de-
scriptor in the ring and the poll time has elapsed and
RXON = 1.
Buffer
Data
Data
1
1
RMD
Rcv Descriptor
N
TMD
M
Xmt Descriptor
Ring
RMD
Buffer
Buffer
N
TMD
Data
Data
Ring
2
2
M
RMD
N
TMD
M
2nd
desc.
2nd
desc.
RMD0
N
TMD
M
•
Buffer
Buffer
Data
Data
•
•
M
N
•
•
•
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