AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 95

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

AMD Flash Programming
AMD’s Flash products are programmed on a byte-by-
byte basis. Programming is a four bus cycle operation.
There are two “unlock” write cycles. These are followed
by the program set-up command and data write cycles.
Addresses are latched on the falling edge of EBWE
and the data is latched on the rising edge of EBWE.
The rising edge of EBWE begins programming.
Upon executing the AMD Flash Embedded Program
Algorithm command sequence, the Am79C973/
Am79C975 controller is not required to provide further
controls or timing. The AMD Flash product will compli-
ment EBD[7] during a read of the programmed location
until the programming is complete. The host software
should poll the programmed address until EBD[7]
matches the programmed value.
AMD Flash byte programming is allowed in any se-
quence and across sector boundaries. Note that a data
0 cannot be programmed back to a 1. Only erase oper-
ations can convert zeros to ones. AMD Flash chip
erase is a six-bus cycle operation. There are two unlock
write cycles, followed by writing the set-up command.
Two more unlock cycles are then followed by the chip
erase command. Chip erase does not require the user
to program the device prior to erasure. Upon executing
the AMD Flash Embedded Erase Algorithm command
Byte Program
Sector Erase
Command
Chip Erase
Sequence
Cycles
Req’d
Write
Bus
4
6
6
EBUA_EBA[7:0]
5555h
5555h
5555h
EBDA[15:8]
Addr
Write Cycle
AS_EBOE
First Bus
EROMCS
EBD[7:0]
Figure 45. Flash Write from Expansion Bus Data Port
EBWE
CLK
Data
AAh
AAh
AAh
Table 12. Am29Fxxx Flash Command
2AAAh
2AAAh
2AAAh
Second Bus
Addr
Write Cycle
P R E L I M I N A R Y
Am79C973/Am79C975
EBUA[19:16]
1
Data
55H
55H
55H
2
5555h
5555h
5555h
3
Addr
Write Cycle
Third Bus
4
sequence, the Flash device will program and verify the
entire memory for an all zero data pattern prior to elec-
trical erase. The Am79C973/Am79C975 controller is
not required to provide any controls or timings during
these operations. The automatic erase begins on the
rising edge of the last EBWE pulse in the command se-
quence and terminates when the data on EBD[7] is 1,
at which time the Flash device returns to the read
mode. Polling by the Am79C973/Am79C975 controller
is not required during the erase sequence. The follow-
ing FLASH programming-table excerpt (Table 12)
shows the command sequence for byte programming
and sector/chip erasure on an AMD Flash device. In
the following table, PA and PD stand for programmed
address and programmed data, and SA stands for sec-
tor address.
The Am79C973/Am79C975 controller will support only
a single sector erase per command and not concurrent
sector erasures. The Am79C973/Am79C975 controller
will support most FLASH devices as long as there is no
timing requirement between the completion of com-
mands. The FLASH access time cannot be guaranteed
with the Am79C973/Am79C975 controller access
mechanism. The Am79C973/Am79C975 controller will
also support only Flash devices that do not require data
hold times after write operations. See Table 12.
Data
5
A0h
80h
80h
6
5555h
5555h
Addr
Write Cycle
Fourth Bus
7
EBDA[15:8]
PA
EBA[7:0]
8
Data
AAh
AAh
9
PD
10
2AAAh
2AAAh
Addr
Write Cycle
11
Fifth Bus
12 13
Data
55h
55h
5555h
Addr
Write Cycle
SA
Sixth Bus
21510D-50
Data
10h
3h
95