AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 58

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

Descriptor DMA Transfers
Am79C973/Am79C975 microcode will determine when
a descriptor access is required. A descriptor DMA read
will consist of two data transfers. A descriptor DMA
write will consist of one or two data transfers. The de-
scriptor DMA transfers within a single bus mastership
period will always be of the same type (either all read
or all write).
During descriptor read accesses, the byte enable sig-
nals will indicate that all byte lanes are active. Should
some of the bytes not be needed, then the Am79C973/
Am79C975 controller will internally discard the extra-
neous information that was gathered during such a
read.
The settings of SWSTYLE (BCR20, bits 7-0) and
BREADE (BCR18, bit 6) affect the way the Am79C973/
Am79C975 controller performs descriptor read opera-
tions.
When SWSTYLE is set to 0 or 2, all descriptor read op-
erations are performed in non-burst mode. The setting
of BREADE has no effect in this configuration. See Fig-
ure 25.
When SWSTYLE is set to 3, the descriptor entries are
ordered to allow burst transfers. The Am79C973/
Am79C975 controller will perform all descriptor read
operations in burst mode, if BREADE is set to 1. See
Figure 26.
Table 5 shows the descriptor read sequence.
During descriptor write accesses, only the byte lanes
which need to be written are enabled.
If buffer chaining is used, accesses to the descriptors
of all intermediate buffers consist of only one data
transfer to return ownership of the buffer to the system.
When SWSTYLE (BCR20, bits 7-0) is cleared to 0 (i.e.,
the descriptor entries are organized as 16-bit software
structures), the descriptor access will write a single
byte. When SWSTYLE (BCR20, bits 7-0) is set to 2 or
3 (i.e., the descriptor entries are organized as 32-bit
software structures), the descriptor access will write a
single word. On all single buffer transmit or receive de-
scriptors, as well as on the last buffer in chain, writes to
the descriptor consist of two data transfers.
The first data transfer writes a DWord containing status
information. The second data transfer writes a byte
(SWSTYLE cleared to 0), or otherwise a word contain-
ing additional status and the ownership bit (i.e.,
MD1[31]).
The settings of SWSTYLE (BCR20, bits 7-0) and
BWRITE (BCR18, bit 5) affect the way the Am79C973/
Am79C975 controller performs descriptor write opera-
tions.
58
P R E L I M I N A R Y
Am79C973/Am79C975
When SWSTYLE is set to 0 or 2, all descriptor write op-
erations are performed in non-burst mode. The setting
of BWRITE has no effect in this configuration.
When SWSTYLE is set to 3, the descriptor entries are
ordered to allow burst transfers. The Am79C973/
Am79C975 controller will perform all descriptor write
operations in burst mode, if BWRITE is set to 1. See
Table 6 for the descriptor write sequence.
A write transaction to the descriptor ring entries is the
only case where the Am79C973/Am79C975 controller
inserts a wait state when being the bus master. Every
data phase in non-burst and burst mode is extended by
one clock cycle, during which IRDY is deasserted.
Note that Figure 26 assumes that the Am79C973/
Am79C975 controller is programmed to use 32-bit soft-
ware structures (SWSTYLE = 2 or 3). The byte enable
signals for the second data transfer would be 0111b, if
the device was programmed to use 16-bit software
structures (SWSTYLE = 0).
SWSTYLE
BCR20[7:0]
0
2
3
3
Table 5. Descriptor Read Sequence
BREADE
BCR18[6]
X
X
0
1
AD Bus Sequence
Address = XXXX XX00h
Turn around cycle
Data = MD1[31:24],
MD0[23:0]
Idle
Address = XXXX XX04h
Turn around cycle
Data = MD2[15:0], MD1[15:0]
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Idle
Address = XXXX XX00h
Turn around cycle
Data = MD0[31:0]
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Idle
Address = XXXX XX08h
Turn around cycle
Data = MD0[31:0]
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Data = MD0[31:0]