AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 127

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

Bit
31-16
15-13
12
11
10
9
8
7
6
Name
RES
RES
MISSM
MERRM
RINTM
TINTM
IDONM
RES
DXSUFLO
zeros and read as undefined.
written as zero.
set, the MISS bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
MISSM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
is set, the MERR bit will be
masked and unable to set the
INTR bit.
Read/Write accessible always.
MERRM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
is set, the RINT bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
RINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
TINTM is set, the TINT bit will be
masked and unable to set the
INTR bit.
Read/Write accessible always.
TINTM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
IDONM is set, the IDON bit will be
masked and unable to set the
INTR bit.
Read/Write accessible always.
IDONM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
written as zeros.
flow error.
Description
Reserved locations. Written as
Reserved locations. Read and
Missed Frame Mask. If MISSM is
Memory Error Mask. If MERRM
Receive Interrupt Mask. If RINTM
Transmit
Initialization
Reserved location. Read and
Disable Transmit Stop on Under-
Interrupt
Done
P R E L I M I N A R Y
Mask.
Mask.
Am79C973/Am79C975
If
If
5
LAPPEN
When DXSUFLO (CSR3, bit 6) is
set to 0, the transmitter is turned
off when an UFLO error occurs
(CSR0, TXON = 0).
When DXSUFLO is set to 1, the
Am79C973/Am79C975 controller
gracefully
UFLO error. It scans the transmit
descriptor ring until it finds the
start of a new frame and starts a
new transmission.
Read/Write accessible always.
DXSUFLO
H_RESET or S_RESET and is
not affected by STOP.
Setting LAPPEN to a 1 also en-
ables the Am79C973/Am79C975
controller to read the STP bit of
receive
Am79C973/Am79C975 controller
will use the STP information to
determine where it should begin
writing a receive packet’s data.
Note that while in this mode, the
Am79C973/Am79C975 controller
can write intermediate packet
data to buffers whose descriptors
do not contain STP bits set to 1.
Following the write to the last de-
scriptor used by a packet, the
Am79C973/Am79C975 controller
will scan through the next de-
scriptor entries to locate the next
STP bit that is set to a 1. The
Am79C973/Am79C975 controller
will begin writing the next packets
data to the buffer pointed to by
that descriptor.
Note that because several de-
scriptors may be allocated by the
Look Ahead Packet Processing
Enable. When set to a 1, the
LAPPEN bit will
Am79C973/Am79C975 controller
to generate an interrupt following
the descriptor write operation to
the first buffer of a receive frame.
This interrupt will be generated in
addition to the interrupt that is
generated following the descrip-
tor write operation to the last buff-
er of a receive packet. The
interrupt will be signaled through
the RINT bit of CSR0.
recovers
descriptors.
is
cleared
cause the
from
127
The
an
by