AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 262

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

2
1
0
SMIU Receive Address Register (MReg Address
39)
Bit No. Name and Description
7:0
262
elapsed. The Am79C975 controller will not re-
try
MTX_LCOL is valid while MTX_START is set
to 0. MTX_LCOL is cleared by H_RESET.
MTX_LCAR
Default: 0
Transmit Loss of Carrier indicates that the
transceiver was in Link Fail state during the
transmission of the alert frame. MTX_LCAR is
valid
MTX_LCAR is cleared by H_RESET.
MTX_RTRY
Default: 0
Transmit Retry error indicates that the trans-
mission of the alert frame has failed after 16 at-
tempts, due to repeated collisions on the
network.
MTX_START is set to 0. MTX_RTRY is
cleared by H_RESET.
MTX_ERR
Default: 0
Transmit Error is the OR of the MTX_LCOL,
MTX_LCAR
MTX_ERR is valid while MTX_START is set to
0. MTX_ERR is cleared by H_RESET.
MRX_ADR
Default: 00h Read/Write
The SMIU Receive Address register contains
the address within the Receive Data memory
from where the next byte of data is read. The
register is cleared to 0 by H_RESET and by
setting MRX_ENABLE in the Receive Status
register, which also unprotects the Receive
Data memory from being overwritten with a
new frame. The address register autoincre-
ments with every byte read from the Receive
Data memory. This allows a FIFO-type access
to the Receive Data memory and the host does
not need to keep track of the location he is
reading from. In addition, MRX_ADR can be
set to any address within the Receive Data
memory in order to modify a specific location.
the
while
transmission
MTX_RTRY
Read only, write has no effect.
Read only, write has no effect.
Read only, write has no effect.
MTX_START
and
MTX_RTRY
on
is
is
late
valid
set
P R E L I M I N A R Y
Am79C973/Am79C975
collision.
to
error.
while
0.
SMIU Receive Data Port (MReg Address 40)
Bit No. Name and Description
7:0
SMIU Receive Message Length Register (MReg
Address 41)
Bit No. Name and Description
7:0
SMIU Receive Status Register (MReg Address 42)
Bit No. Name and Description
7
6:3
MRX_DATA
Default: undefinedRead only, write has no ef-
fect.
This is the 8-bit data port used to read from the
Receive Data memory.
MRX _LEN
Default: undefinedRead only, write has no ef-
fect.
The SMIU Receive Message Length contains
the length of the acknowledgment frame, in-
cluding FCS. MRX_LEN only contains valid in-
formation after the Am79C975 controller has
set the MRX_DONE bit in the Interrupt regis-
ter. A message length value of larger than 128
indicates, that the Receive Data memory has
overflowed. A message length between 129
and 132 bytes indicates that only FCS bytes
have been lost and all message data bytes are
available in the Receive Data memory. A mes-
sage length greater than 132 indicates that
message data bytes have been lost from the
end of the message and the host should dis-
card the frame. MRX_LEN will indicate the cor-
rect message length up to 255 bytes. It will
freeze at 255 for longer frames. MRX_LEN is
not affected by H_RESET.
MRX_ENABLE
Default: 0
When MRX_ENABLE is set to a 1, the
Am79C975 controller is enabled to receive ac-
knowledgment frames from the management
station. The host must program the acknowl-
edgment frame filter registers with valid data
before
MRX_ENABLE to a 1 will also clear the Re-
ceive Pattern RAM Address and Receive Ad-
dress
automatically cleared after every receive.
MRX_ENABLE is cleared by H_RESET.
RESERVED
setting
registers.
Read/Write
MRX_ENABLE.
MRX_ENABLE
Setting
is