AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 44

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

During the boot procedure, the system will try to find an
Expansion ROM. A PCI system assumes that an Ex-
pansion ROM is present when it reads the ROM signa-
ture 55H (byte 0) and AAH (byte 1).
Slave Cycle Termination
There are three scenarios besides normal completion
of a transaction where the Am79C973/Am79C975 con-
trollers are the target of a slave cycle and it will termi-
nate the access.
Disconnect When Busy
The Am79C973/Am79C975 controllers cannot service
any slave access while it is reading the contents of the
EEPROM. Simultaneous access is not allowed in order
to avoid conflicts, since the EEPROM is used to initial-
ize some of the PCI configuration space locations and
most of the BCRs and CSR116. The EEPROM read
operation will always happen automatically after the
deassertion of the RST pin. In addition, the host can
start the read operation by setting the PREAD bit
(BCR19, bit 14). While the EEPROM read is on-going,
the Am79C973/Am79C975 controllers will disconnect
any slave access where it is the target by asserting
STOP together with DEVSEL, while driving TRDY high.
STOP will stay asserted until the end of the cycle.
Note that I/O and memory slave accesses will only be
disconnected if they are enabled by setting the IOEN or
MEMEN bit in the PCI Command register. Without the
enable bit set, the cycles will not be claimed at all.
Since H_RESET clears the IOEN and MEMEN bits for
the automatic EEPROM read after H_RESET, the dis-
connect only applies to configuration cycles.
A second situation where the Am79C973/Am79C975
controllers will generate a PCI disconnect/retry cycle is
when the host tries to access any of the I/O resources
right after having read the Reset register. Since the ac-
cess generates an internal reset pulse of about 1 ms in
length, all further slave accesses will be deferred until
the internal reset operation is completed. See Figure 6.
Disconnect Of Burst Transfer
The Am79C973/Am79C975 controllers do not support
burst access to the configuration space, the I/O re-
sources, or to the Expansion Bus. The host indicates a
burst transaction by keeping FRAME asserted during
the data phase. When the Am79C973/Am79C975 con-
trollers see FRAME and IRDY asserted in the clock
cycle before it wants to assert TRDY, it also asserts
STOP at the same time. The transfer of the first data
phase is still successful, since IRDY and TRDY are
both asserted. See Figure 7.
44
P R E L I M I N A R Y
Am79C973/Am79C975
Figure 7. Disconnect Of Slave Burst Transfer - No
Figure 6. Disconnect Of Slave Cycle When Busy
DEVSEL
FRAME
DEVSEL
FRAME
TRDY
STOP
IRDY
C/BE
TRDY
STOP
CLK
PAR
IRDY
C/BE
CLK
PAR
AD
AD
1
1
Host Wait States
ADDR
CMD
1st DATA
2
BE
2
PAR
PAR
3
DATA
3
BE
DATA
4
BE
PAR
4
PAR
5
21510D-11
21510D-12
5