AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 142

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

CSR31: Base Address of Transmit Ring Upper
Bit
31-16
15-0
CSR32: Next Transmit Descriptor Address Lower
Bit
31-16
15-0
CSR33: Next Transmit Descriptor Address Upper
Bit
31-16
15-0
CSR34: Current Transmit Descriptor Address
Lower
Bit
31-16
142
Name
RES
BADXU
Name
RES
NXDAL
Name
RES
NXDAU
Name
RES
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
base address of the Transmit
Ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
next transmit descriptor address
pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
next transmit descriptor address
pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
P R E L I M I N A R Y
Am79C973/Am79C975
15-0
CSR35: Current Transmit Descriptor Address
Upper
Bit
31-16 RES
15-0
CSR36: Next Next Receive Descriptor Address
Lower
Bit
31-16 RES
15-0
CSR37: Next Next Receive Descriptor Address
Upper
Bit
31-16 RES
15-0
CXDAL
Name
CXDAU
Name
NNRDAL
Name
NNRDAU
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
current transmit descriptor ad-
dress pointer.
Description
Reserved locations. Written as
zeros and read as undefined.
current transmit descriptor ad-
dress pointer.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
next next receive descriptor ad-
dress pointer.
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
next next receive descriptor ad-
dress pointer.
Contains the lower 16 bits of the
Contains the upper 16 bits of the