AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 273

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

ler will not perform any power-consuming DMA opera-
tions. However, external circuitry can still respond to
control frames on the network to facilitate remote node
control. Table C-69 summarizes the operation of the
EADI interface.
When using the MII, the data arrives in nibbles and can
be at a rate of 25 MHz or 2.5 MHz.
The MII provides all necessary data and clock signals
needed for the EADI interface. Data for the EADI is the
RXD(3:0) receive data provided to the MII. RX_CLK is
provided to allow clocking of the RXD(3:0) receive nib-
ble stream into the external address detection logic.
The RXD(3:0) data is synchronous to the rising edge of
the RX_CLK.
The assertion of SFBD is a signal to the external ad-
dress detection logic that the SFD has been detected
and that the first valid data nibble is on the RXD(3:0)
data bus. The SFBD signal is delayed one RX_CLK
cycle from the above definition and actually signals the
start of valid data. In order to reduce the amount of
logic external to the Am79C973/Am79C975 controller
for multiple address decoding systems, the SFBD sig-
nal will go HIGH at each new byte boundary within the
packet, subsequent to the SFD. This eliminates the
need for externally supplying byte framing logic.
The EAR pin should be driven LOW by the external ad-
dress comparison logic to reject a frame.
External Address Detection Interface: Receive
Frame Tagging
The Am79C973/Am79C975 controller supports re-
ceive frame tagging in the MII mode. The receive frame
PROM
1
0
0
EAR
X
1
0
Table 69. EADI Operations
No timing
requirements
No timing
requirements
Low for two bit
times plus 10 ns
Required
MIIRXFRTGD
MIIRXFRTGE
Timing
RX_CLK
RX_DV
SFBD
All received frames
All received frames
Frame rejected if in
address match
mode
Figure 79. MII Receive Frame Tagging
Received
Frames
P R E L I M I N A R Y
Am79C973/Am79C975
tagging implementation will be a two--wire chip inter-
face, respectively, added to the existing EADI.
The Am79C973/Am79C975 controller supports up to
15 bits of receive frame tagging per frame in the receive
frame status (RFRTAG). The RFRTAG bits are in the
receive frame status field in RMD2 (bits 30-16) in 32-bit
software mode. The receive frame tagging is not sup-
ported in the 16-bit software mode. The RFRTAG field
are all zeros when either the EADISEL (BCR2, bit3) or
the RXFRTAG (CSR7, bit 14) are set to 0. When
EADISEL (BCR2, bit 3) and RXFRTAG (CSR7, bit 14)
are set to 1, then the RFRTAG reflects the tag word
shifted in during that receive frame.
In the MII mode, the two-wire interface will use the
MIIRXFRTGD and MIIRXFRTGE pins from the EADI
interface. These pins will provide the data input and
data input enable for the receive frame tagging, respec-
tively. These pins are normally not used during the MII
operation.
The receive frame tag register is a shift register that
shifts data in MSB first, so that less than the 15 bits al-
located may be utilized by the user. The upper bits not
utilized will return zeros. The receive frame tag register
is set to 0 in between reception of frames. After receiv-
ing SFBD indication on the EADI, the user can start
shifting data into the receive tag register until one net-
work clock period before the Am79C973/Am79C975
controller receives the end of the current receive frame.
In the MII mode, the user must see the RX_CLK to
drive the synchronous receive frame tag data interface.
After receiving the SFBD indication, sampled by the ris-
ing edge of the RX_CLK, the user will drive the data
input and the data input enable synchronous with the
rising edge of the RX_CLK. The user has until one net-
work clock period before the deassertion of the RX_DV
to input the data into the receive frame tag register. At
the deassertion of the RX_DV, the receive frame tag
register will no longer accept data from the two-wire in-
terface. If the user is still driving the data input enable
pin, erroneous or corrupted data may reside in the re-
ceive frame tag register. See Figure C-79.
21510C-79
273