AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 153

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

27-12 PARTID
11-1
0
CSR89: Chip ID Register Upper
Bit
31-16 RES
15-12 VER
MANFID
ONE
Am79C973
Am79C975
Name
Device
VER is read only. Write opera-
tions are ignored.
Part number. The 16-bit code for
the
0010 0110 0010 0101 (2625h)
and the code for the Am79C975
is 0010 0110 0010 0111 (2627h).
Manufacturer ID. The 11-bit man-
ufacturer
00000000001b. This code is per
the JEDEC Publication 106-A.
Always a logic 1.
Reserved locations. Read as un-
defined.
Version. This 4-bit pattern is
silicon-revision dependent.
This register is exactly the same
as the Device ID register in the
JTAG description. However, this
part number is different from that
stored in the Device ID register in
the PCI configuration space.
Read accessible only when either
the STOP or the SPND bit is set.
PARTID is read only. Write oper-
ations are ignored.
Note that this code is not the
same as the Vendor ID in the PCI
configuration space.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. MANFID is
read only. Write operations are
ignored.
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. ONE is read
only. Write operations are ig-
nored.
Description
Am79C973
code
CSR88
5003h
7003h
for
controller
P R E L I M I N A R Y
Am79C973/Am79C975
AMD
is
is
11-0
CSR92: Ring Length Conversion
Bit
31-16 RES
15-0
CSR100: Bus Timeout
Bit
31-16 RES
15-0
PARTIDU
RCON
MERRTO
Name
Name
Ring Length Conversion Regis-
This register contains the value of
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. VER is read
only. Write operations are ig-
nored.
Upper 12 bits of the Am79C973/
Am79C975 controller part num-
ber, i.e., 0010 0110 0010b
(262h).
Read accessible only when either
the STOP or the SPND bit is set.
VER is read only. PARTIDU is
read only. Write
ignored.
Reserved locations. Written as
zeros and read as undefined.
ter. This register performs a ring
length conversion from an encod-
ed value as found in the initializa-
tion block to a two’s complement
value used for internal counting.
By writing bits 15-12 with an en-
coded ring length, a two’s com-
plemented value is read. The
RCON register is undefined until
written.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Reserved locations. Written as
zeros and read as undefined.
the longest allowable bus latency
(interval between assertion of
REQ and assertion of GNT) that a
system
Am79C973/Am79C975 controller
master transfer. If this value of
bus latency is exceeded, then a
MERR will be indicated in CSR0,
bit 11, and an interrupt may be
generated, depending upon the
Description
Description
may
insert
operations are
into
153
an