AM79C973BKD\W AMD (ADVANCED MICRO DEVICES), AM79C973BKD\W Datasheet - Page 136

• Manufacturer Part Number: AM79C973BKD\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKD\W

• Lead Free Status / RoHS Status: Compliant

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MCCIINT
MCCIINTE PHY Management Command
MIIPDTINT PHY Detect Transition Interrupt.
through the MAPINT (CSR7, bit
6) interrupt or the MCCIINTE is
set to 1.
Read/Write accessible always.
MCCINTE
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Complete Internal Interrupt. The
PHY
Complete Interrupt is set by the
Am79C973/Am79C975 controller
when a read or write operation on
the internal PHY management
port is complete from an internal
operation. Examples of internal
operations are Auto-Poll or PHY
Management
management frames. These are
normally hidden to the host.
When MCCIINT is set to 1, INTA
is asserted if the enable bit MC-
CINTE is set to 1.
Read/Write accessible always.
MCCIINT is cleared by the host
by writing a 1. Writing a 0 has no
effect. MCCIINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Complete Internal Interrupt En-
able. If MCCIINTE is set to 1, the
MCCIINT bit will be able to set
the INTR bit when the internal
state machines generate man-
agement frames. For instance,
when MCCIINTE is set to 1 and
the Auto-Poll state machine gen-
erates a management frame, the
MCCIINT will set the INTR bit
upon completion of the manage-
ment frame regardless of the
comparison outcome.
Read/Write accessible always.
MCCIINTE
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
The PHY Detect Transition Inter-
PHY Management Command
Management
is
is
Port
set
set
P R E L I M I N A R Y
to
Command
to
generated
Am79C973/Am79C975
0
0
by
by
0
CSR8: Logical Address Filter 0
Bit
31-16 RES
15-0
CSR9: Logical Address Filter 1
Bit
31-16 RES
15-0 LADRF[31:16] Logical Address Filter, LADRF-
LADRF[15:0] Logical Address Filter, LADRF-
MIIPDTINTE PHY Detect Transition Interrupt
Name
Name
Read/Write accessible always.
MIIPDTINT is cleared by the host
by writing a 1. Writing a 0 has no
effect. MIIPDTINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Read/Write accessible always.
MIIPDTINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
rupt is set by the Am79C973/
Am79C975 controller whenever
the MIIPD bit (BCR32, bit 14)
transitions from 0 to 1 or vice ver-
sa.
Enable. If MIIPDTINTE is set to 1,
the MIIPDTINT bit will be able to
set the INTR bit.
Description
Reserved locations. Written as
zeros and read as undefined.
[15:0]. The content of this register
is undefined until loaded from the
initialization block after the INIT
bit in CSR0 has been set or a di-
rect register write has been per-
formed on this register.
Description
Reserved locations. Written as
zeros and read as undefined.
[31:16]. The content of this regis-
ter is undefined until loaded from
the initialization block after the
INIT bit in CSR0 has been set or
a direct register write has been
performed on this register.